Type 6 Carrier Board Design Guide ’s Carrier Board Design Guide COM Express Type 6 Module Carrier Board Design Guide User Manual Page I Rev. 1.
Type 6 Carrier Board Design Guide Revision Date Version Changes 1 August, 2013 1.01 Modified Section 4.5: AT Power Delivery Guideline 15 March, 2013 1.
Type 6 Carrier Board Design Guide Copyright COPYRIGHT NOTICE The information in this document is subject to change without prior notice in order to improve reliability, design and function and does not represent a commitment on the part of the manufacturer. In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.
Type 6 Carrier Board Design Guide Table of Contents 1 INTRODUCTION.......................................................................................................... 1 1.1 INTRODUCTION........................................................................................................... 2 1.2 ICE-QM770 COM EXPRESS MODULE ....................................................................... 2 1.2.1 ICE-QM770 Specifications ........................................................................
Type 6 Carrier Board Design Guide 3.3 SATA (SERIAL ATA INTERFACE)............................................................................ 33 3.3.1 Signal Description ........................................................................................... 33 3.3.2 SATA Connector............................................................................................... 34 3.3.3 SATA LED#...................................................................................................... 34 3.3.
Type 6 Carrier Board Design Guide 3.9.1 Signal Description ........................................................................................... 53 3.9.2 Giga LAN Connector ....................................................................................... 54 3.9.3 LAN Link Activity and Speed LED................................................................... 55 3.9.4 LAN Routing Guideline.................................................................................... 55 3.9.4.1 Impedance .
Type 6 Carrier Board Design Guide 4.4.2 ATX Power Diagram........................................................................................ 72 4.5 AT POWER DELIVERY GUIDELINE ........................................................................... 72 5 MECHANICAL DESIGN GUIDELINES ................................................................. 73 5.1 CHAPTER OVERVIEW ................................................................................................ 74 5.
Type 6 Carrier Board Design Guide List of Figures Figure 1-1: ICE-QM770 ...................................................................................................................2 Figure 1-2: ICE-CV-D25501/N26001...............................................................................................4 Figure 1-3: ICE-DB-T6 ....................................................................................................................7 Figure 2-1: COM Express Type 6 Module Diagram .......
Type 6 Carrier Board Design Guide Figure 3-27: VGA Connector D-SUB15 .......................................................................................60 Figure 3-28: VGA Reference Design ...........................................................................................62 Figure 3-29: Speaker Out Reference Schematic .......................................................................64 Figure 3-30: RTC Reference Schematic .....................................................................
Type 6 Carrier Board Design Guide List of Tables Table 1-1: ICE-QM770 Specifications ...........................................................................................4 Table 1-2: ICE-CV-D25501/N26001 Specifications.......................................................................6 Table 1-3: ICE-DB-T6 Specifications.............................................................................................9 Table 2-1: COM Express Connector Type Variations ...................................
Type 6 Carrier Board Design Guide Chapter 1 1 Introduction Page 1
Type 6 Carrier Board Design Guide 1.1 Introduction This design guide describes the design concept of the COM Express Type 6 module and teaches customers how to develop their own COM Express carrier board. The IEI COM Express Type 6 module is compatible with all baseboards compliant with COM Express specification. 1.2 ICE-QM770 COM Express Module Figure 1-1: ICE-QM770 The ICE-QM770 COM Express module provides the main processing chips and is connected to a compatible COM Express baseboard.
Type 6 Carrier Board Design Guide 1.2.1 ICE-QM770 Specifications The ICE-QM770 technical specifications are listed below. Specifications/Model ICE-QM770 PICMG COM Express R2.0 Type 6 for basic size Form Factor CPU Socket CPU Supported Express Chipset (95 mm x 125 mm) Socket G2 2nd and 3rd generation Intel® Core™ i7/i5/i3, Pentium® and Celeron® processors Intel® QM77 Two 204-pin 1600/1333/1066 MHz dual-channel Memory DDR3/DDR3L (1.35V) SO-DIMMs supported (system max.
Type 6 Carrier Board Design Guide Specifications/Model ICE-QM770 I/O Interfaces (Signal to Baseboard) Four USB 3.0 8-bit GPIO Eight USB 2.0 SMBus Two SATA 6Gb/s I2C Two SATA 3Gb/s LPC Two RS-232 TPM HD Audio SPI +12V @ 1.75 A , Vcore_12V @ 3.33A (2.
Type 6 Carrier Board Design Guide The ICE-CV-D25501/N26001 COM Express module provides the main processing chips and is connected to a compatible COM Express baseboard. The ICE-CV-D25501/N26001 is equipped with an Intel® Atom™ D2550/N2600 CPU and Intel® NM10 PCH. The COM Express standard allows the COM Express baseboard to be designed, while leaving the choice of processor till the later stages of design. The ICE-CV-D25501/N26001 provides a low power option with the full range of modern I/O options.
Type 6 Carrier Board Design Guide Specifications/Model ICE-CV-D25501/N26001 BIOS UEFI BIOS USB 3.0 ASMedia ASM1042 Embedded Controller iWDD Watchdog Timer Software programmable supports 1~255 sec. system reset Expansion Four PCIe x1 (signal to baseboard) Two USB 3.0 Eight USB 2.0 Two SATA 3Gb/s Two UART (by EC) HD Audio I/O Interfaces (Signal to Baseboard) GPIO SMBus I2C LPC SPI Power Consumption Operating Temperature +12V @ 0.45 A , Vcore_12V @ 1.0A (1.
Type 6 Carrier Board Design Guide 1.4 ICE-DB-T6 Reference Carrier Board The ICE-DB-T6 is a full function carrier board for customers to apply or test the COM Express Type 6 module. The carrier board can be used for any combination, including software and hardware. Using the carrier board to develop and test the Type 6 module also can achieve a quicker time to market. The ICE-DB-T6 is shown in Figure 1-3 and the specifications are listed in Table 1-3. Figure 1-3: ICE-DB-T6 1.4.
Type 6 Carrier Board Design Guide Specifications/Model ICE-DB-T6 Reference Carrier Board Audio Realtek ALC892 HD Audio codec GPIO 8-bit GPIO (GPIO from iWDD co-lay SDIO) Watchdog Timer Software programmable supports1~255 sec.
Type 6 Carrier Board Design Guide Specifications/Model ICE-DB-T6 Reference Carrier Board 1 x VGA 4 x USB 3.0 1 x RJ-45 GbE External I/O 2 x DisplayPort 3 x Audio jacks (Line-in, Line-out, Mic) 1 x PS/2 keyboard 1 x PS/2 mouse Power Supply Operating Temperature ATX/AT power supply -10ºC ~ 60ºC Storage Temperature -20ºC ~ 70ºC Humidity (Operating) 5% ~ 95% (non-condensing) Dimensions 304.8 mm x 243.8 mm (12” x 9.
Type 6 Carrier Board Design Guide Chapter 2 2 Pin Assignments Page 10
Type 6 Carrier Board Design Guide 2.1 Chapter Overview This chapter describes pin assignments and I/O characteristics for COM Express modules. The carrier board uses two 220-pin 0.5 mm fine pitch board-to-board connectors. There are seven different pin-out types currently defined by the COM Express Specification. The preferred choice of the embedded computer industry is the Type 2 pin-out and the latest pin-outs added in COM Express specification are Type 6 and Type 10.
Type 6 Carrier Board Design Guide 2.2 COM Express Connector Type The differences among the Module Types are summarized in Table 2-1. Module Type 1 and 10 supports a single connector with two rows of pins (220 pins total). Module Types 2-6 support two connectors with four rows of pins (440 pins total). Type Rows PCIe PEG/ Lanes SDVO PCI IDE SATA LAN USB Display 2.0/3.
Type 6 Carrier Board Design Guide 2.3 Signal Table Terminology The following section describes the signals found on the Type 6 connectors. Table 2-2 below describes the terminology used in this section for the Signal Description tables. The “#” symbol at the end of the signal name indicates that the active or asserted state occurs when the signal is at a low voltage level. When “#” is not present, the signal is asserted when at a high voltage level.
Type 6 Carrier Board Design Guide 2.
Type 6 Carrier Board Design Guide Pin A46 A47 A48 A49 A50 Signal USB0+ VCC_RTC EXCD0_PERST# EXCD0_CPPE# LPC_SERIRQ I/F USB PWR PCIE PCIE LPC A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 A70 A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 A81 A82 A83 A84 A85 A86 A87 A88 A89 A90 A91 A92 GND5 PCIE_TX5+ PCIE_TX5GPI0 PCIE_TX4+ PCIE_TX4GND6 PCIE_TX3+ PCIE_TX3GND7 PCIE_TX2+ PCIE_TX2GPI1 PCIE_TX1+ PCIE_TX1GND8 GPI2 PCIE_TX0+ PCIE_TX0GND9 LVDS_A0+ LVDS_A0LVDS_A1+ LVDS_A1LVDS_A2+ LVDS_A2LVD
Type 6 Carrier Board Design Guide Pin A93 A94 A95 A96 A97 A98 A99 A100 A101 A102 A103 A104 A105 A106 A107 A108 A109 A110 Signal GPO0 SPI_CLK SPI_MOSI PP_TPM RSVD RS1_TX RS1_RX GND13 RS2_TX RS2_RX LID# VCC_12V7 VCC_12V8 VCC_12V9 VCC_12V10 VCC_12V11 VCC_12V12 GND14 I/F GPIO SPI SPI TPM UART UART GND UART UART PWR PWR PWR PWR PWR PWR GND I/O O O IO I O I O I I - Pin B93 B94 B95 B96 B97 B98 B99 B100 B101 B102 B103 B104 B105 B106 B107 B108 B109 B110 Signal VGA_HSYNC VGA_VSYNC VGA_I2C_CK VGA_I2C_DAT SPI_CS#
Type 6 Carrier Board Design Guide Pin C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 C43 C44 C45 C46 C47 C48 C49 C50 C51 C52 C53 C54 C55 C56 C57 C58 C59 C60 C61 C62 C63 C64 C65 C66 C67 C68 C69 C70 C71 C72 C73 Signal DDI1_PAIR4RSVD RSVD DDI1_PAIR5+ DDI1_PAIR5GND3 DDI2_AUX+ DDI2_AUXDDI2_CTRLCLK RSVD DDI3_AUX+ DDI3_AUXDDI3_CTRLCLK DDI3_PAIR0+ DDI3_PAIR0GND4 DDI3_PAIR1+ DDI3_PAIR1DDI3_HPD RSVD DDI3_PAIR2+ DDI3_PAIR2RSVD DDI3_PAIR3+ DDI3_PAIR3GND5 PEG_RX0+ PEG_RX0RSVD PEG_RX1+ PEG_RX1RSVD P
Type 6 Carrier Board Design Guide Pin C74 C75 C76 C77 C78 C79 C80 C81 C82 C83 C84 C85 C86 C87 C88 C89 C90 C91 C92 C93 C94 C95 C96 C97 C98 C99 C100 C101 C102 C103 C104 C105 C106 C107 C108 C109 C110 Signal PEG_RX7+ PEG_RX7GND8 RSVD4 PEG_RX8+ PEG_RX8GND10 PEG_RX9+ PEG_RX9RSVD5 GND6 PEG_RX10+ PEG_RX10GND35 PEG_RX11+ PEG_RX11GND27 PEG_RX12+ PEG_RX12GND11 PEG_RX13+ PEG_RX13GND12 RSVD6 PEG_RX14+ PEG_RX14GND13 PEG_RX15+ PEG_RX15GND VCC_12V1 VCC_12V2 VCC_12V3 VCC_12V4 VCC_12V5 VCC_12V6 GND14 Page 18 I/F PEG PEG G
Type 6 Carrier Board Design Guide Chapter 3 3 Signal Description and Routing Guideline Page 19
Type 6 Carrier Board Design Guide 3.1 PEG (PCI Express Graphic) The PEG Port can utilize COM Express PCIe lanes 16 through 32 to drive a PCIe x16 link for a PCI Express Graphics card. It supports a theoretical bandwidth of up to 4 GB/s. Each lane of the PEG Port consists of a receiver and transmit differential signal pair. The corresponding signals can be found on the Module connector rows C and D. 3.1.
Type 6 Carrier Board Design Guide D81 D82 C85 C86 D85 D86 C88 C89 D88 D89 C91 C92 D91 D92 C94 C95 D94 D95 C98 C99 D98 D99 C101 C102 D101 D102 A88 A89 D54 PEG_TX9+ PEG_TX9PEG_RX10+ PEG_RX10PEG_TX10+ PEG_TX10PEG_RX11+ PEG_RX11PEG_TX11+ PEG_TX11PEG_RX12+ PEG_RX12PEG_TX12+ PEG_TX12PEG_RX13+ PEG_RX13PEG_TX13+ PEG_TX13PEG_RX14+ PEG_RX14PEG_TX14+ PEG_TX14PEG_RX15+ PEG_RX15PEG_TX15+ PEG_TX15PCIE_CLK_REF + PCIE_CLK_REFPEG_LANE_RV# D97 PEG_ENABLE# O PEG Port 9. Transmit Output differential pair. I PEG Port 10.
Type 6 Carrier Board Design Guide 3.1.2 PEG Connector Figure 3-1 illustrates the pinout definition for the standard PCI Express x16 connectors. +V3.3 +V12 +V12 +V3.
Type 6 Carrier Board Design Guide 3.1.3 PEG_ENABLE# PEG_ENABLE# is defined on the COM Express connector as a method to configure the COM Express PCIe lanes 16 through 32 on the C-D connector as a PCI Express Graphics port for an external graphics device. The usual effect of pulling PEG_ENABLE# low is to disable the on-Module graphics engine.
Type 6 Carrier Board Design Guide Figure 3-2: Intel Recommend Test Structure for PCI Express Data Eye Measurement 3.1.5 PCI Express Routing Guideline 3.1.5.1 Impedance Consideration The PCI Express impedance considerations are listed in Table 3-2.
Type 6 Carrier Board Design Guide Length matching between RX and TX pairs (inter-pair) Length matching between reference clock differential pairs REFCLK+ and REFCLK(intra-pair) Length matching between reference clock pairs (inter-pair) Reference plain Spacing from edge of plane Via Usage AC coupling capacitors No strict electrical requirements. Keep difference within a 3.0 inch delta to minimize latency. Max. 5mils No electrical requirements. GND referenced preferred Min. 40mils Max.
Type 6 Carrier Board Design Guide PEG SLOT or SDVO Device TX+ TX- ICE Module AC Coupling Cap RX+ RX- Figure 3-3: PEG Lane Connection Topology Example 3.1.5.3 Routing Notices Each signal and its complement in a differential pair should be length matched whenever possible on a segment-by-segment basis at the point of discontinuity. Examples of segments might include breakout areas, routes to connect vias, routes to connect an AC coupling capacitor, routes to connect a connector, and so forth.
Type 6 Carrier Board Design Guide Preferred Routing Alternative Routing Bad Routing Preferred Routing Preferred Routing Figure 3-4: PEG Layout Trace Example 3.2 PCI Express PCI Express provides a scalable, high-speed, serial I/O point-to-point bus connection. A PCI Express lane consists of dual simplex channels, each implemented as a low-voltage differentially driven transmit pair and receive pair. They are used for simultaneous transmission in each direction.
Type 6 Carrier Board Design Guide The PCI Express interface of the COM Express module consists of up to six lanes, each with a receive and transmit differential signal pair. According to the PCI Express specification, these six lanes can be configured as several PCI Express x1 links or to a combined x4 link plus two x1 links. These configuration possibilities are based on the COM Express module's chipset capabilities. 3.2.
Type 6 Carrier Board Design Guide 3.2.2 PCI Express x1 Slot Table 3-3 illustrates the pinout definition for the standard PCI Express x1 connector. The dashed lines in the diagram depict where each different connector type ends. +V3.3 +V12 +V12 +V3.
Type 6 Carrier Board Design Guide 1 1 TP96 3 TP97 3 PCIE_RX3+ PCIE_RX3- 4 CLK33M_MINICARD 3,6,10,11,14,20 CB_RESET# PCIE_TX3+ PCIE_TX30_4 2 0_4 2 1 R122 1 R123 0_4 2 0_4 2 1 R70 1 R72 4 CLK100M_PCIEx1_SLOT4+ 4 CLK100M_PCIEx1_SLOT4TP40 3,6,10,16 PCIE_WAKE_UP# 1 PCIE_WAKE_UP# 15 13 11 9 7 5 3 1 GND2 REFCLK+ REFCLKGND1 CLKREQ# RESERVED_2 RESERVED_1 WAKE# 53 CN1(LATCH)1 +V3.
Type 6 Carrier Board Design Guide 9 7 5 3 1 GND CLKREQ# Reserved**** Reserved**** WAKE# 10 8 6 4 2 Reserved** Reserved** 1.5V GND 3.3V * Reserved for future second PCI Express Lane (if needed) ** Reserved for future Subscriber Identity Module (SIM) interface (if needed) *** Reserved for future wireless disable signal (if needed) **** Reserved for future wireless coexistence control interface (if needed) Table 3-4: Mini Card Pin-out Figure 3-7: Mini Card Bottom Side Dimensions (Refer to www.pcisig.
Type 6 Carrier Board Design Guide Figure 3-8: Mini Card Top Side Dimensions (Refer to www.pcisig.com) Figure 3-9: Mini Card Connector (Refer to www.pcisig.com) 3.2.4 PCI Express Clock Buffer COM Express only provides a set of 100 MHz clock for PCI Express device. When there are more than one PCI Express modules used on the carrier board, the clock buffer must be used. Please refer to the schematic diagram (Figure 3-10) suggested by IEI.
Type 6 Carrier Board Design Guide +V3.3_CLK_A +V3.3_CLK +V3.
Type 6 Carrier Board Design Guide A26 A22 A23 B25 B26 B22 B23 A28 SATA2_RXSATA2_TX+ SATA2_TXSATA3_RX+ SATA3_RXSATA3_TX+ SATA3_TXSATA_ACT# O SATA Serial ATA channel 2 Transmit output differential pair. I SATA Serial ATA channel 3 Receive input differential pair. O SATA Serial ATA channel 3 Transmit output differential pair. O 3.3V CMOS OC Serial ATA activity LED. Open collector output pin driven during SATA command activity. Table 3-5: Serial ATA Signal Descriptions 3.3.
Type 6 Carrier Board Design Guide +V3.3 R322 4.7K R323 4.7K D17 HDD_LED# 11,21 HDD_LED# 3,21 ATA_ACT# K1 K2 1 LED1 3 C C A R324 470_6_5% +V5 LEDRED_8_2 2 BAW56LT1_SOT23 Figure 3-12: SATA LED Connection Example 3.3.
Type 6 Carrier Board Design Guide 3.4 Universal Serial Bus (USB) The Universal Serial Bus (USB) provides a bi-directional, isochronous, hot-attachable Plug and Play serial interface for external peripheral devices. A COM Express Module provides a minimum of four USB ports and can support up to eight USB 2.0 ports and four USB 3.0 ports. The USB physical topology consists of connecting the downstream hub port to the upstream port of another hub or to a device. The USB can operate at three speeds.
Type 6 Carrier Board Design Guide B38 USB_4_5_OC# I 3.3V CMOS A38 USB_6_7_OC# I 3.3V CMOS C4 C3 D4 D3 C7 C6 D7 D6 C10 C9 D10 D9 C13 C12 D13 D12 USB_SSRX0+ USB_SSRX0USB_SSTX0+ USB_SSTX0USB_SSRX1+ USB_SSRX1USB_SSTX1+ USB_SSTX1USB_SSRX2+ USB_SSRX2USB_SSTX2+ USB_SSTX2USB_SSRX3+ USB_SSRX3USB_SSTX3+ USB_SSTX3- I PCIe O PCIe I PCIe O PCIe I PCIe O PCIe I PCIe O PCIe a USB current monitor on the Carrier Board may drive this line low. Do not pull this line high on the Carrier Board.
Type 6 Carrier Board Design Guide Figure 3-13: Keyed Connector Protocol (Refer to USB2.0 Spec.) The following list explains how the plugs and receptacles can be mated: Series “A” receptacle mates with a Series “A” plug. Electrically, Series “A” receptacles function as outputs from host systems and/or hubs. Series “A” plug mates with a Series “A” receptacle. The Series “A” plug always is oriented towards the host system. Series “B” receptacle mates with a Series “B” plug (male).
Type 6 Carrier Board Design Guide Pin Signal I/O Description 1 VCC P +5V Power supply 2 DATA- I/O USB Data, negative differential signal. 3 DATA+ I/O USB Data, positive differential signal. 4 GND P Ground Table 3-8: USB Connector Signal Description 3.4.3 ESD/EMI To improve the EMI behavior of the USB interface, common mode choke should be included in a design.
Type 6 Carrier Board Design Guide 3.4.4 Over Current Protection Over-current protection for USB ports can be implemented by using power distribution switches on the carrier board that monitor the USB port power lines. Power distribution switches usually have a soft-start circuitry that minimizes inrush current in applications where highly capacitive loads are employed. Transient faults are internally filtered.
Type 6 Carrier Board Design Guide adjacent to the USB Port connector pins. The OC# signal is asserted until the over-current or over-temperature condition is resolved. USB0+/- through USB4+/- from the COM Express Module are routed through a common mode choke to reduce radiated cable emissions. The part shown is a AXIS POWER BCCUB-T4P-2012-900T; this device has a common mode impedance of approximately 90 Ω at 100MHz. The common-mode choke should be placed close to the USB connector.
Type 6 Carrier Board Design Guide 3.4.6 USB Routing Guideline 3.4.6.1 Impedance Parameters Routing Transfer rate / Port 480 Mbit/s Maximum signal line length (coupled traces) Max. 17.0 inches Signal length used on COM Express module (including the COM Express" connector) " Signal length allowance for the COM Express carrier board " 3.0 inches 14.0 inches Differential Impedance 90 Ohms +/-15% Single-ended Impedance 45 Ohms +/-10% Spacing between pairs-to-pairs (inter-pair) (s) Min.
Type 6 Carrier Board Design Guide layers with USB 2.0 traces as much as practical. It is preferable to change layers to avoid crossing a plane split. USB 2.0 traces as much as practical. It is preferable to change layers to avoid crossing a plane split. Separate signal traces into similar categories, and route similar signal traces together (such as routing differential pairs together). Keep USB 2.0 signals clear of the core logic set.
Type 6 Carrier Board Design Guide C43 C46 C47 C49 C50 D15 D16 DDI3_PAIR1DDI3_PAIR2+ DDI3_PAIR2DDI3_PAIR3+ DDI3_PAIR3DDI1_AUX+ DDI1_AUX- C32 C33 DDI2_AUX+ DDI2_AUX- I 3.3V CMOS C36 C37 DDI3_AUX+ DDI3_AUX- I 3.3V CMOS C73 DDI1_CTRLDATA I/O D34 DDI2_CTRLDATA I/O D38 DDI3_CTRLDATA I/O D73 DDI1_CTRLCLK I/O C34 DDI2_CTRLCLK I/O C38 DDI3_CTRLCLK I/O C24 DDI1_HPD D44 DDI2_HPD C44 DDI3_HPD O PCIe DDI 3. Transmit Output differential pair 2. O PCIe DDI 3.
Type 6 Carrier Board Design Guide 3.5.2 DDI Pins and Video Interfaces The table below provides the mapping between the DDI pins and the different types of video interfaces supported by COM Express Type 6 modules. Pin No.
Type 6 Carrier Board Design Guide C38 D38 C36 C37 DDI3_CTRLCLK DDI3_CTRLDATA DDI3_AUX+ DDI3_AUX- DP3_AUX+ DP3_AUX- HDMI3_CTRLCLK HDMI3_CTRLDATA Table 3-10: DDI Pins and Video Interfaces Mapping 3.5.2.1 DDI Signal Description: SDVO Signal SDVO1_RED+ SDVO1_REDSDVO1_GRN+ SDVO1_GRNSDVO1_BLU+ SDVO1_BLUSDVO1_CK+ SDVO1_CKSDVO1_INT+ SDVO1_INTSDVO1_TVCLKIN+ SDVO1_TVCLKINSDVO1_FLDSTALL+ SDVO1_FLDSTALLSDVO1_CTRLCLK SDVO1_CTRLDATA I/O Description O PCIe Serial Digital Video red output differential pair.
Type 6 Carrier Board Design Guide 3.5.2.3 DDI Signal Description: HDMI/DVI Signal I/O TMDS[1:3]_DATA[0:2]+ TMDS[1:3]_DATA[0:2]TMDS[1:3]_CLK+ TMDS[1:3]_CLKHDMI[1:3]_HPD HDMI[1:3]_CTRLCLK O PCIe O PCIe I I/O 3.3V CMOS I/O 3.3V CMOS HDMI[1:3]_CTRLDATA Description HDMI/DVI TMDS lanes 0, 1 and 2 differential pairs. HDMI/DVI TMDS Clock differential pair. HDMI/DVI hot-plug detect HDMI/DVI I2C control clock HDMI/DVI I2C control data Table 3-13: DDI Signal Descriptions – HDMI/DVI 3.6 LVDS 3.6.
Type 6 Carrier Board Design Guide A83 LVDS_I2C_CK A84 LVDS_I2C_DAT CMOS O 3.3V CMOS I/O 3.3V OD CMOS DDC I2C clock signal used for flat panel detection and control. DDC I2C data signal used for flat panel detection and control. Table 3-14: LVDS Signals Description 3.6.2 LVDS Cable Consideration Balanced cables (twisted pair) are usually better than unbalanced cables (ribbon cable) for noise reduction and signal quality. Balanced cables provide a low-cost solution with good balance and flexibility.
Type 6 Carrier Board Design Guide LVDS +V3.3 C109 10U_8_X_6V3 J_VLVDS1 C110 10U_8_X_6V3 J_VLVDS1 +V12 5V R145 C269 1000P_4_X_50V 1 2 R417 100K_4 C273 2.2U_6_Y _10V 2 G S HEADER_1X3_2 7 8 Q3 2N7002_SOT23 C270 0.1U_4_Y _16V 1 S G 3 LVDS_VDD_EN 1 Q2A FDS6975_SOP8 D D 2 1M_4 +V3.3_LCD_PANEL 3 +V5 2 1 2-3 1 +V3.3 2 1 3.3V(Default) 1 1-2 R151 C271 0.1U_4_Y _16V 2 J_VLVDS1(1-2) MINIJUMPER_1X2_2 +V5 C272 10U_1210_Y_25V 2 100K_4 Figure 3-19: LVDS Power Control C114 C115 0.
Type 6 Carrier Board Design Guide Figure 3-21: LCD Power Sequence Example (Refer to AUO G150XG01) 3.6.4 LVDS Routing Guideline 3.6.4.1 Impedance Parameters Transfer Rate Maximum signal line length to the LVDS connector (coupled traces) Signal length used on COM Express module (including the COM Express" carrier board connector) " Signal length to the LVDS connector available for the COM Express carrier board " Differential Impedance Page 50 Routing 5.38 Gbits/sec 8.75 inches 2.0 inches 6.
Type 6 Carrier Board Design Guide Single-ended Impedance 55 Ohms +/-15% Spacing between pair to pairs (inter-pair) (s) Min. 20mils Spacing between differential pairs and high-speed periodic signals Spacing between differential pairs and low-speed non periodic signals Min. 20mils Min.
Type 6 Carrier Board Design Guide Pin Signal I/O Description A30 AC_RST# O 3.3VSB CMOS CODEC Reset. A29 AC_SYNC O 3.3V CMOS A32 A33 B30 B29 B28 AC_BITCLK AC_SDOUT AC_SDIN0 AC_SDIN1 AC_SDIN2 O 3.3V CMOS O 3.3V CMOS I 3.3VSB CMOS 48kHz fixed-rate, sample-synchronization signal to the CODEC(s). 12.228 MHz Serial Bit Clock for CODEC. Serial TDM data output to the CODEC. Serial TDM data inputs from up to 3 CODECs Table 3-16: Audio Signals Description 3.
Type 6 Carrier Board Design Guide 3.8.1.2 Digital and Analog Signals Isolation Analog audio signals and other digital signals should be routed as far as possible from each other. All audio circuits require careful PCB layout and grounding to avoid picking up digital noise on audio-signal lines. 3.8.1.
Type 6 Carrier Board Design Guide A3 A2 GBE0_MDI3+ GBE0_MDI3- I/O A14 GBE0_CTREF REF A8 GBE0_LINK# A4 GBE0_LINK100# A5 GBE0_LINK1000 # B2 GBE0_ACT# O 3.3V CMOS O 3.3V CMOS O 3.3V CMOS O 3.3V CMOS 10Mbit/sec modes. Media Dependent Interface (MDI) differential pair 3. The MDI can operate in 1000, 100, and 10Mbit/sec modes. Reference voltage for carrier board Ethernet channel 0 magnetics center tap.
Type 6 Carrier Board Design Guide 3.9.3 LAN Link Activity and Speed LED The COM Express module has four 3.3V open drain outputs to directly drive activity, speed indication and link status LEDs. The 3.3V standby voltage should be used as LED supply voltage so that the link activity can be viewed during system standby state. Since LEDs are likely to be integrated into a RJ-45 connector with integrated magnetics module, the LED traces need to be routed away from potential sources of EMI noise. 3.9.
Type 6 Carrier Board Design Guide 3.9.4.2 LAN Ground Plane Separation Isolated separation between the analog ground plane and digital ground plane is recommended. If they are not implemented properly then bad ground plane partitioning could cause serious EMI emissions and degrade analog performance due to bouncing noise. The plane area underneath the magnetic module should be left void. The void area is to keep transformer induced noise away from the power and system ground planes.
Type 6 Carrier Board Design Guide Pin Signal I/O Description A50 LPC_SERIRQ LPC serialized IRQ. B3 LPC_FRAME# B4 B5 B6 B7 B8 B9 B10 LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_DRQ0# LPC_DRQ1# LPC_CLK I/O 3.3V CMOS O 3.3V CMOS I/O 3.3V CMOS I 3.3V CMOS O 3.3V CMOS LPC encoded DMA/Bus master request. LPC frame indicates start of a new cycle or termination of a broken cycle. LPC multiplexed command, address and data. LPC clock output 33MHz. Table 3-19: LPC Interface Signal Descriptions 3.10.
Type 6 Carrier Board Design Guide Figure 3-24: Windbond W83627DHG Reference Design 3.10.2.1 Keyboard/Mouse The following figures display reference circuitries for the legacy I/O interfaces connected to the Winbond W83627HG Super I/O controller, including PS/2 keyboard/mouse and RS-232 serial ports. The PS/2 connector has to be powered up by the +5V standby voltage to support keyboard and mouse wake up functionality from low power system states (S1 and S3).
Type 6 Carrier Board Design Guide F1 2 +V5_DUAL FB5 +V5_KB_R 1 FB19_6_500MA FUSE_12_1.
Type 6 Carrier Board Design Guide 3.11.1 Signal Description Table 3-20 shows COM Express VGA signals, including pin number, signals, I/O, power plane, terminal resistors, damping resistors and descriptions. Pin D-SUB15 Signal I/O Description B89 1 VGA_RED O Analog B91 2 VGA_GRN O Analog B92 3 VGA_BLU O Analog B93 13 VGA_HSYNC B94 14 VGA_VSYNC B95 15 VGA_I2C_CK O 3.3V CMOS O 3.3V CMOS I/O 3.3V CMOS Red component of analog DAC monitor output, designed to drive a 37.
Type 6 Carrier Board Design Guide 3.11.4 Routing Guide Line 3.11.4.1 HSYNC and VSYNC Signals The horizontal and vertical sync signals 'VGA_HSYNC' and 'VGA_VSYNC' provided by the COM Express module are 3.3V tolerant outputs. It is necessary to implement high impedance unidirectional buffers since VGA monitors may drive the monitor sync signals with 5V tolerance.
Type 6 Carrier Board Design Guide IO_GND A K +V3.3 D1 +V3.3 IO_GND C123 10P_4_N_50V C124 22P_4_N_50V 1 2 G 2 12 CRT_DDCDATA R160 13 CRT_HSY NC R162 1 2 33_4 14 CRT_VSY NC R164 1 2 33_4 15 CRT_DDCCLK R165 1 2 33_4 1 2 33_4 VGA_I2C_DAT_Z R161 1 VGA_I2C_DAT 2 0_4 +V3.3 VGA_I2C_DAT VGA_HSY NC VGA_VSYNC VGA_I2C_CK_Z R166 1 2 0_4 IO_GND VGA_I2C_CK +V3.3 IO_GND K C L7 FB47_6_300MA R157 @2.
Type 6 Carrier Board Design Guide B66 B67 WAKE0# WAKE1# I CMOS I CMOS A27 B35 BATLOW# THRM# I CMOS I CMOS A35 THERMTRIP# O CMOS B102 B101 B13 B14 FAN_TACHOIN FAN_PWMOUT SMB_C SMB_DAT I CMOS O CMOS I/O 3.3V OD CMOS B15 SMB_ALERT# I 3.3V CMOS B33 B34 B32 I2C_CK I2C_DAT SPKR I/O 3.
Type 6 Carrier Board Design Guide 3.12.2 Speaker/FAN Control/RTC Reference 3.12.2.1 Speaker Out +V5 R321 Buzzer +V5S_BUZZER 33_4 SP1 SATG1205NP45_DIP12X10_6.5 C C246 0.1U_4_Y_16V 1 2 3,18,21 2 2.7K_4 E 1 R325 SPKR B Q14 2N3904_SOT23 Figure 3-29: Speaker Out Reference Schematic 3.12.2.2 RTC Q10,C234 and R304 are for the no battery solution. Using super CAP to instead of Battery. Q10 CLEAR CMOS/Super CAP A1 C 1 +V3.3_DUAL 1K_4 A2 2 BAT54C SOT23_AAC R304 JP9(1-2) JUMP_1X2_2.
Type 6 Carrier Board Design Guide 3.12.2.
Type 6 Carrier Board Design Guide Chapter 4 4 PCB Stack and Power Deliver Design Page 66
Type 6 Carrier Board Design Guide 4.1 Chapter Overview A brief description of the Printed Circuit Board (PCB) for COM Express based board is provided in this section. From a cost- effectiveness point of view, a four-layer board is the target platform for the motherboard design. For better quality, a six-layer or 8-layer board is preferred. This chapter also provides the ATX/AT power supply design recommendation for customer’s reference. IEI ICE module carrier board use 4-layer PCB stack. 4.
Type 6 Carrier Board Design Guide 4.3.1 Four-Layer Stack-up Figure 4-1 below is an example of a four layer stack-up. Layers L1 and L4 are used for signal routing. Layers L2 and L3 are used for solid ground and power planes respectively. Microstrips on Layers 1 and 4 reference ground and power planes on Layers 2 and 3 respectively. It may be advantageous to swap the GND and PWR planes in some cases. This allows Layer 4 to be GND referenced.
Type 6 Carrier Board Design Guide and 5 respectively. Inner Layer 3 and Layer 4 are asymmetric striplines that are referenced to planes on Layers 2 and Layer 5. Figure 4-2: Six-Layer Stack NOTE: All high-speed signals should reference solid ground planes through the length of their routing and should not cross plane splits. To guarantee this, both planes surrounding strip-lines should be GND.
Type 6 Carrier Board Design Guide strip-line layers. For high-speed signals transitioning between layers next to the component, the signal pins should be accounted for by the GND stitching vias that would stitch all the GND plane layers in that area of the board. High-speed routing on external layers should be minimized in order to avoid EMI. Routing on external layers also introduces different delays compared to internal layers.
Type 6 Carrier Board Design Guide 4.4.1 ATX Power States (S0, S3, S4, S5, G3) The ATX power source will provide 12V, -12V, 5V, -5V, 3.3V and 5VSB power, if other voltage (3.3VSB, LAN1.8V…. ) is required on the carried board. The additional switching regulator or LDO will be necessary. Power states are described below: State Description Comment G3 Mechanical Off AC power to system is removed, by a mechanical switch.
Type 6 Carrier Board Design Guide 4.4.2 ATX Power Diagram Battery(3.3V) +12V COM-Express Module +5VSB ATX Power Source LD O +3.3VSB +5V +3.3V -12V -5V Figure 4-3: ATX Power Delivery Block Diagram 4.5 AT Power Delivery Guideline The AT power source will provide 12V and 5V power. The additional switching regulator or LDO will be required to simulate the ATX power (3.3V…). The AT power deliver diagram is shown below.
Type 6 Carrier Board Design Guide Chapter 5 5 Mechanical Design Guidelines Page 73
Type 6 Carrier Board Design Guide 5.1 Chapter Overview The interconnection between COM Express modules and the carrier board uses two 220-pin 0.5mm fine pitch board-to-board connectors. Each 220-pin connector is split into two connector rows and results in a total of 440 pins and four connector rows. These connectors should be capable of driving up to 6.25GHz Low Voltage Differential Signals to meet the requirements for PCI Express signaling. 5.2 COM Module and Carrier Board Connector 5.2.
Type 6 Carrier Board Design Guide Figure 5-1: Module Connector Picture 5.2.2 Carrier Board Connector The single 220-pin 0.5mm pitch carrier board connectors are 5H/8H plug in connectors with a board-to-board stack height of 5.0mm/8.0mm. A potential source for this plug-in board-to-board connector is: 3-1827253-6 AMP/Tyco HARD TRAY ASSY FH 0.5 BTB CONNECTOR 220POS PLUG 5H WITH GROUND PLATE (5.0mm stack height) 8-1318491-6 AMP/Tyco HARD TRAY ASSY FH 0.5 BTB CONNECTOR 220POS PLUG 8H WITH GROUND PLATE (8.
Type 6 Carrier Board Design Guide 5.3 Connector Footprint It is essential that the distance and the alignment of the dual connector shape on the PCB comply to the dimensions defined by the COM Express Specification. The alignment between the two single connectors is guaranteed by the connectors peg holes shown in following drawings. It is very important that the PCB drill tolerances of these peg holes are within the recommended ranges mentioned below.
Type 6 Carrier Board Design Guide The COM Express PnP Initiative strongly recommends to use the following location peg hole tolerances instead of those indicated in the footprint drawings from the COM Express Specification as shown above: • 0.8mm +0.075/-0.025mm • 1.5mm +0.075/-0.025mm 5.4 COM Express Form Factors COM Express specifies four form factors, as well as seven different types of connector pinouts. The four form factors are referred to as Mini, Compact, Basic and Extended.
Type 6 Carrier Board Design Guide Figure 5-5: Compact, Basic and Extended Form Factor 5.5 Heat Spread One of the important factors for the system integration is the thermal design. The heatspreader, usually a 3mm thick aluminum plate, acts as a thermal coupling device to the Module. The heatspreader is thermally coupled to the CPU via a thermal gap filler and on some Modules it may also be thermally coupled to other heat generating components with the use of additional thermal gap fillers.
Type 6 Carrier Board Design Guide Figure 5-6: Overall Height for Heatspreader in Basic and Extended Modules All dimensions in mm. Tolerances (unless otherwise specified): Z (height) dimensions should be ± 0.8mm [±0.031”] from top of carrier board to top of heatspreader. Heatspreader surface should be flat within 0.2mm [.008"] after assembly. Interface surface finish should have a maximum roughness average (Ra) of 1.6μm [63μin].
Type 6 Carrier Board Design Guide Figure 5-8: Basic Module Heatspreader Footprint All dimensions are in mm. X-Y tolerances shall be ± 0.3mm [±0.012"]. The interior holes at coordinates (40, 40) and (80, 40) are tapped through holes with a M2.5 thread. The interior holes do not receive standoffs. These holes may be sealed on the module side by an adhesive backed foil, or they may be blind tapped holes with a minimum thread depth of 2.5 mm.
Type 6 Carrier Board Design Guide Figure 5-9: IEI Heat Spread Module 5.6 Design Notes 5.6.1 Component Height — Module Back and Carrier Board Top Parts mounted on the backside of the module (in the space between the bottom surface of the module PCB and the carrier board) shall have a maximum height of 3.8 mm (dimension ‘B’ in Figure 5-10). With the 5 mm stack option, the clearance between the carrier board and the bottom surface of the module’s PCB is 5 mm (dimension ‘A’ in Figure 5-10).
Type 6 Carrier Board Design Guide Figure 5-10: Component Clearances Underneath Module 5.6.2 Air Follow Issue The air flow of the IEI COM Express fan module must be considered when installing a COM Express system. Please refer to Figure 5-10 for air flow consideration. 5.6.3 Grounding Issue The mounting holes on all ICE COM modules are connected to digital circuit ground (GND) for improved EMC performance.
Type 6 Carrier Board Design Guide chassis ground through the heat sink andor heatspreader. System designers should take this into account when defining system grounding. 5.7 Others Kits Specification 5.7.1 Cooling Kit IEI provides a standard cooling kit specially designed for the COM Express Type 6 modules. The cooling kit includes a heatspreader plate and a heat sink. The cooling kit dimensions and photos are shown below.
Type 6 Carrier Board Design Guide Appendix A A Terminology Page 84
Type 6 Carrier Board Design Guide Terminology Description AC97 Audio Codec 97 (AC’97) refers to a codec standard developed by Intel® in 1997. HDA High Definition Audio SATA Serial ATA (SATA) is a serial communications bus designed for data transfers between storage devices and the computer chipsets. EMI Electromagnetic Interference ESD Electrostatic Discharge PCIe x1, x2, x4, x16 x1 refers to one PCI Express Lane of basic bandwidth; x2 to two PCI Express Lanes; etc..
Type 6 Carrier Board Design Guide PAL Phase Alternate Line PCI Peripheral Component Interface RTC Real Time Clock SMBus System Management Bus. COM Computer On Module STD Suspend To Disk STR Suspend To RAM ULV Ultra-Low Voltage USB Universal Serial Bus N.C. Not connected N.A. Not available T.B.D.
Type 6 Carrier Board Design Guide Appendix B B Application Notes Page 87
Type 6 Carrier Board Design Guide NOTE: IEI is able to provide customers with the ICE module design guide and information as well as many other application notes. IEI will keep the ICE module information most updated. Please contact IEI for the latest design guide and related information. B.1 Terminology Some of the following terms may be used throughout this section. Term Description BIOS Basic Input Output System.
Type 6 Carrier Board Design Guide Figure B-1: BIOS Main Menu (BIOS Version: MR10) B.2.1 Using AFUWIN To use AFUWIN application to update the BIOS version, follow the steps below. Step 1: Install and launch AFUWIN. Step 2: Click Open button to open the BIOS file.
Type 6 Carrier Board Design Guide Step 3: Locate the BIOS file that needs to be updated. Figure B-3: Locate BIOS File Step 4: Check ”Program All Block” option. Figure B-4: Check Program All Block Step 5: Click Flash button to start updating BIOS.
Type 6 Carrier Board Design Guide Figure B-5: AFUWIN – Flash Step 6: Restart the system and check the BIOS menu. The BIOS version is changed to MR11.
Type 6 Carrier Board Design Guide B.2.2 Using DOS Command To update BIOS in the DOS environment, prepare a USB flash drive that contains boot files and BIOS updating files shown in the figure below and follow the steps below to update BIOS. Figure B-7: USB Flash Drive and BIOS Updating Files Step 1: Connect the USB flash drive to the system. Boot-up the system into DOS. Input commands to get into the directory of the BIOS updating files (ex. cd (folder name)).
Type 6 Carrier Board Design Guide Step 2: Input command GO and press Enter. The system starts updating BIOS. Figure B-9: GO Command Step 3: The following picture shows the screen when the update is completed.
Type 6 Carrier Board Design Guide Step 4: Restart the system and check the BIOS menu. The BIOS version has been changed to MR11. Figure B-11: BIOS Main Menu – Updated BIOS Version (MR11) B.3 RTC Overview A Real-time clock (RTC) is a basic hardware device that keeps track of the current time of the computer. A RTC can be built in a chip or embedded in the system. When the computer is turned off, the battery on the motherboard provides power to the RTC to keep track of the current time.
Type 6 Carrier Board Design Guide Appendix C C Reference Documents Page 95
Type 6 Carrier Board Design Guide The following table lists all the reference documents of this design guide. Document Location PICMGR COM Express Module™ Base Specification http://www.picmg.org/ I2C Bus Interface http://www.semiconductors.philips.com/ PCI Local Bus Specification, Revision 2.3 http://www.pcisig.com/ Serial ATA Specification, Revision 1.0a http://www.serialata.org/ PC104 http://www.pc104.org/technology/pc104_tech.html SMBus http://www.smbus.
Type 6 Carrier Board Design Guide Appendix D D Reference Carrier Board Schematic Page 97
