Owner's Manual

17
ii) When set WLCK/DARS, the clock port input should have the following corresponding signals:
- When the USB input song frequency is a multiplier of 44100 (44100, 88200, 176400), the
sampling rate supported by the clock input is 40100hz - 48100Hz,
- When the USB input song frequency is 48000 times (48000, 96000, 192000), the clock input
supports sampling rate 44000hz - 52000Hz.
Current USB playback sampling rate is X
- If X% 44100 == 0, the supported input sampling rate: (44100-4000 / (X / 44100)) ~ (44100 + 4000 / (X / 44100))
- If X% 48000 == 0, the supported input sampling rate: (48000-4000 / (X / 48000)) ~ (48000 + 4000 / (X / 48000))
- %: remained
3) Passive Filtering and Discrete Analogue stage
Each d/a converter operates in the 'voltage output mode', giving >119dB dynamic range. All ltering is passive.
A fully-balanced 3rd order capacitor/inductor/capacitor lter is used to remove ultrasonic noise directly after the
d/a conversion rather than active, feedback-based circuits.
Active lters struggle with the amount of ultrasonic noise and RFI they have to handle and at a few 100kHz they
often lose the ability to lter noise at all, which is precisely where a lot of it is present.
Passive CLC circuitry in the Pro iDSD Signature provides the correct ltering well into the MHz region, so that the
follow-on analogue stage is not required to handle ultrasonic noise and RFI originating within the DAC processes.
An all-analogue six-track Japanese Alps potentiometer is to be found directly after DAC and lter stages. It can
be bypassed if volume control is not required.
The actual analogue circuitry is more precisely a line/headphone driver stage. First seen in the Pro iCAN, it's fully
balanced and 100% discrete, direct-coupled (without coupling capacitors) and tube/solid-state user-selectable.
Our design is not just op-amp based discrete but radically dierent - pure Class A topology. It was inspired by
exceptional sounding, legendary studio equipment.