Data Sheet, Rev.1.
BTS4175SGA 1 Overview 3 2 Block Diagram 5 3 3.1 3.2 3.3 Pin Configuration 6 Pin Assignment 6 Pin Definitions and Functions 6 Voltage and Current Definition 7 4 4.1 4.2 4.3 General Product Characteristics 8 Absolute Maximum Ratings 8 Functional Range 9 Thermal Resistance 9 5 5.1 5.2 5.3 5.4 Power Stage 10 Output ON-State Resistance 10 Turn ON / OFF Characteristics 10 Inductive Output Clamp 11 Electrical Characteristics Power Stage 13 6 6.1 6.2 6.3 6.4 6.5 6.
Smart High-Side Power Switch 1 BTS4175SGA Overview Basic Features • • • • • • • • • • Fit for 12V and 24V application One Channel device Very Low Stand-by Current CMOS Compatible Inputs Electrostatic Discharge Protection (ESD) Optimized Electromagnetic Compatibility Logic ground independent from load ground Very Low Leakage Current from OUT to the load in OFF state Green Product (RoHS compliant) AEC Qualified PG-DSO-8-24 Description The BTS4175SGA is a single channel Smart High-Side Power Switch.
BTS4175SGA Overview Protection Functions • • • • • • • Short circuit protection Overload protection Current limitation Thermal shutdown Overvoltage protection (including load dump) with external resistor Loss of ground and loss of battery protection Electrostatic discharge protection (ESD) Application • All types of relays, lamps and resistive loads Data Sheet 4 Rev.1.
BTS4175SGA Block Diagram 2 Block Diagram VS voltage sensor internal power supply over temperature driver logic IN gate control & charge pump E SD protection T clamp for inductive load over current switch off open load detection OUT ST GND Figure 1 Data Sheet Block diagram .emf Block diagram for the BTS4175SGA 5 Rev.1.
BTS4175SGA Pin Configuration 3 Pin Configuration 3.1 Pin Assignment GND 1 8 VS IN 2 7 VS OUT 3 6 VS ST 4 5 VS Figure 2 Pin Configuration 3.2 Pin Definitions and Functions Pin Symbol Function 1 GND Ground; Ground connection 2 IN Input channel; Input signal. Activate the channel in case of logic high level 3 OUT Output; Protected High side power output channel 4 ST Diagnostic feedback; of channel. Open drain.
BTS4175SGA Pin Configuration 3.3 Voltage and Current Definition Figure 3 shows all terms used in this data sheet, with associated convention for positive values. IS VS VD S VS IIN IN IL OUT VIN VOU T IST ST V ST GND R GND I GN D Voltage and current convention single avec diag.vsd Figure 3 Data Sheet Voltage and current definition 7 Rev.1.
BTS4175SGA General Product Characteristics 4 General Product Characteristics 4.1 Absolute Maximum Ratings Absolute Maximum Ratings 1) TJ = 25°C; (unless otherwise specified) Pos. Parameter Symbol Limit Values Unit Conditions Min. Max. – 52 V – 0 52 V – 0 36 V RECU = 20mΩ, RCable=16mΩ/m, LCable=1µH/m, Voltages VS - VS(REV) 4.1.1 Supply voltage 4.1.2 Reverse polarity Voltage 4.1.3 Supply voltage for short circuit protection Vbat(SC) l = 0 or 5m 2) see Chapter 6 Input pins 4.
BTS4175SGA General Product Characteristics 4.2 Pos. 4.2.1 Functional Range Parameter Symbol Limit Values Min. Max. Unit Conditions Operating Voltage VSOP 6 52 V VIN = 4.5V, RL = 47Ω, VDS < 0.5V VSUV IGND – 5.5 V – 2 mA VIN = 5V IS(OFF) – – 15 18 µA Tj <85°C Tj = 150°C, RL = 47Ω, VIN = 0V 4.2.2 Undervoltage shutdown 4.2.3 Operating current 4.2.
BTS4175SGA Power Stage 5 Power Stage The power stage is built by an N-channel vertical power MOSFET (DMOS) with charge pump. 5.1 Output ON-State Resistance The ON-state resistance RDS(ON) depends on the supply voltage as well as the junction temperature Tj. Figure 4 shows the dependencies for the typical ON-state resistance. The behavior in reverse polarity is described in Chapter 6.4.
BTS4175SGA Power Stage 5.3 Inductive Output Clamp When switching OFF inductive loads with high side switches, the voltage VOUT drops below ground potential, because the inductance intends to continue driving the current. To prevent the destruction of the device due to high voltages, there is a voltage clamp mechanism implemented that keeps the negative output voltage at a certain level (VS-VDS(AZ)). Please refers to Figure 6 and Figure 7 for details.
BTS4175SGA Power Stage VS 2 1 E = --- × LI × ⎛⎝ 1 – ------------------------------------------⎞ 2 V S – V DS ( AZ ) )⎠ The energy, which is converted into heat, is limited by the thermal design of the component. See Figure 8 for the maximum allowed energy dissipation. 1800 1600 1400 EAS(mJ) 1200 1000 800 600 400 200 0 0 0,5 1 Load current (A) Figure 8 Data Sheet 1,5 EAS.vsd Maximum energy dissipation single pulse, Tj,Start = 150 °C; VS = 13.5V 12 Rev.1.
BTS4175SGA Power Stage 5.4 Electrical Characteristics Power Stage Electrical Characteristics: Power stage VS = 13.5 V, Tj = -40 °C to +150 °C,(unless otherwise specified). Typical values are given at Tj = 25°C Pos. Parameter Symbol 5.4.1 ON-state resistance per channel RDS(ON) Limit Values Min. Typ. Max. – 175 – Unit Conditions mΩ Tj=25°C1), IL = 1A, VIN= 5V, See Figure 4 5.4.2 5.4.3 – 280 350 – V TA=85°C1), Tj <150°C1) IDS = 4mA2) 5 µA VIN=0V 0.7 2 V/µs RL=47Ω, Vs=13.
BTS4175SGA Protection Mechanisms 6 Protection Mechanisms The device provides embedded protective functions. Integrated protection functions are designed to prevent the destruction of the IC from fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are designed for neither continuous nor repetitive operation. 6.
BTS4175SGA Protection Mechanisms In the case the supply voltage is in between of VS(SC) max and VDS(AZ), the output transistor is still operational and follow the input. If the channel is in ON state, parameters are no longer warranted and lifetime is reduced compared to normal mode. This specially impacts the short circuit robustness, as well as the maximum energy EAS the device can handle. 6.4 Reverse Polarity Protection In case of reverse polarity, the intrinsic body diode causes power dissipation.
BTS4175SGA Protection Mechanisms IN t IL IL(LIM) IL(SCr) tm t ST TdST(+) t Current limitation with diag full . vsd Figure 11 Data Sheet Current limitation function of the time 16 Rev.1.
BTS4175SGA Protection Mechanisms 6.6 Electrical Characteristics Protection Functions Electrical Characteristics: Protection VS = 13.5 V, Tj = -40 °C to +150 °C. Typical values are given at Tj = 25°C Pos. Parameter Symbol Limit Values Unit Conditions Min. Typ. Max. -VDS(REV) – 600 – mV TJ = 150°C VOUT > VS VS(AZ) 62 – – V Is = 4mA – – 4 – 6.5 – 9 – – A Tj = -40°C, Tj = 25°C, Tj = 150°C VS < 40V1), VS > 40V1) Reverse polarity 6.6.
BTS4175SGA Diagnostic Mechanism 7 Diagnostic Mechanism For diagnosis purpose, the BTS4175SGA provides a status pin. 7.1 ST Pin BTS4175SGA status pin is an open drain, active low circuit. Figure 12 shows the equivalent circuitry. As long as no “hard” failure mode occurs (Short circuit to GND / Over temperature or open load in OFF), the signal is permanently high, and due to a required external pull-up to the logic voltage will exhibit a logic high in the application.
BTS4175SGA Diagnostic Mechanism If the channel is OFF, the output is no longer pulled down by the load and VOUT voltage rises to nearly VS. This is recognized by the device as open load. The voltage threshold is given by VOL(OFF). In that case, the ST signal is switched to a logical low VSTL. Vbat SOL BTS4175SGA VS R OL OUT I LOFF OL comp. R PD Ileakage GND VOL(OFF ) RGND Rleakage Open Load in OFF .
BTS4175SGA Diagnostic Mechanism 7.2.2 ST Signal in case of Over Temperature In case of over temperature, the junction temperature reaches the thermal shutdown temperature TjSC. In that case, the ST signal is stable and remains to toggling between VST(L) and VST(H). Figure 15 gives a sketch of the situation. IN t V OUT t ST t T JSC ΔT JSC TJ t Diagnostic In Overload full toggling.vs Figure 15 Sense signal in overtemperature condition . Data Sheet 20 Rev.1.
BTS4175SGA Diagnostic Mechanism 7.3 Electrical Characteristics Diagnostic Functions Electrical Characteristics: Diagnostics VS = 13.5 V, Tj = -40 °C to +150 °C, (unless otherwise specified) Typical values are given at Vs = 13.5V, Tj = 25°C Pos. Parameter Symbol Limit Values Min. Typ. Max. Unit Conditions Load condition threshold for diagnostic 7.3.1 Open Load detection threshold in OFF state1) VOL(OFF) – 3.0 4.0 V VIN = 0V 7.3.1 Short circuit detection voltage VOUT(SC) – 2.
BTS4175SGA Input Pin 8 Input Pin 8.1 Input Circuitry The input circuitry is CMOS compatible. The concept of the Input pin is to react to voltage transition and not to voltage threshold. With the Schmidt trigger, it is impossible to have the device in an un-defined state, if the voltage on the input pin is slowly increasing or decreasing. The output is either OFF or ON but cannot be in an linear or undefined state. The input circuitry is compatible with PWM applications.
BTS4175SGA Application Information 9 Application Information Note: The following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. VBAT VDD VDD RPUST VBAT_SW R IN Vdd ROL Vs OUT Microcontroller (e.g. XC22xx) IN IN ST OUT RST GND GND R GND Application example single avec diag.
BTS4175SGA Package Outlines 10 Package Outlines 1.27 0.1 0.41 +0.1 -0.05 +0.05 -0.01 0.2 C 0.64 ±0.25 0.2 M A C x8 8 5 Index Marking 1 4 5 -0.21) 8˚ MAX. 4 -0.21) 1.75 MAX. 0.1 MIN. (1.5) 0.33 ±0.08 x 45˚ 6 ±0.2 A Index Marking (Chamfer) 1) Figure 18 Does not include plastic or metal protrusion of 0.15 max.
BTS4175SGA Revision History 11 Revision History Version Date Changes 1.0 2008-03-12 Creation of the data sheet Data Sheet 25 Rev.1.
Edition 2008-04-29 Published by Infineon Technologies AG 81726 Munich, Germany © 2008 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics.
