Datasheet

TLE 6208-6 G
Data Sheet 16 2007-09-12
SPI-Interface
Delay Time from Stand-by to Data In
Setup time t
set
––100µs–
Logic Inputs DI, CLK and CSN
H-input voltage threshold V
IH
––0.7V
CC
–
L-input voltage threshold
V
IL
0.2 – – V
CC
–
Hysteresis of input voltage
V
IHY
50 200 500 mV –
Pull up current at pin CSN
I
ICSN
–50 –25 –10 µA V
CSN
= 0.7 × V
CC
Pull down current at pin DI I
IDI
10 25 50 µA V
DI
= 0.2 × V
CC
Pull down current at pin CLK I
ICLK
10 25 50 µA V
CLK
= 0.2 × V
CC
Input capacitance
at pin CSN, DI or CLK
C
I
– 1015pF0V < V
CC
<
5.25 V
Note: Capacitances are guaranteed by design
Logic Output DO
H-output voltage level
V
DOH
V
CC
– 1.0
V
CC
– 0.7
–VI
DOH
=1 mA
L-output voltage level
V
DOL
– 0.2 0.4 V I
DOL
= – 1.6 mA
Tri-state leakage current
I
DOLK
– 10 – 10 µA V
CSN
= V
CC
0V < V
DO
< V
CC
Tri-state input capacitance C
DO
– 1015pFV
CSN
= V
CC
0V < V
CC
<
5.25 V
Note: Capacitances are guaranteed by design
2.3 Electrical Characteristics (cont’d)
8V<V
S
< 40 V; 4.75 V < V
CC
< 5.25 V; INH = High; all outputs open; – 40 °C<T
j
< 150 °C;
unless otherwise specified
Parameter Symbol Limit Values Unit Test Condition
min. typ. max.