Datasheet

TLE6288R
SPI
Data Sheet 16 Rev. 2.4, 2007-08-08
edge (if CLKProg = L; rising edge if CLKProg = H) of serial clock. It is essential that the SCLK pin is in a logic high
state (if CLKProg = L; low state if CLKProg = H) whenever chip select CS
makes any transition.
SI - Serial Input. Serial data bits are shifted in at this pin, the most significant bit (MSB) first. SI information is read
in on the rising edge of SCLK (if CLKProg = L; falling edge if CLKProg = H). Input data is latched in the SPI shift
register and then transferred to the internal registers of the logic.
The input data consists of 16 bits, made up of 4 control bits and 12 data bits. The control word is used to program
the device, to operate it in a certain mode as well as providing diagnostic information (see Chapter 5.5).
SO - Serial Output. Diagnostic data bits are shifted out serially at this pin, the most significant bit (MSB) first. SO
is in a high impedance state until the
CS
pin goes to a logic low state. New diagnostic data will appear at the SO
pin following the falling edge of SCLK (if CLKProg = L; rising edge if CLKProg = H).
5.2 Electrical Characteristics: SPI Timing
Electrical Characteristics: SPI Timing
V
CC
= 4.5 V to 5.5 V, T
j
= -40 °C to +150 °C, V
B
= 6 V to 16 V, Reset = H, V
DO
= V
CC
, all voltages with respect to
ground, positive current flowing into pin (unless otherwise specified)
Pos. Parameter Symbol Limit Values Unit Pin/
Comment
Conditions
Min. Typ. Max.
5.2.1 Serial Clock Frequency
(depending on SO load)
f
SCLK
DC – 5 MHz – –
5.2.2 Serial Clock Period (1/
f
SCLK
) t
p(SCLK)
200 – – ns – –
5.2.3 Serial Clock High Time
t
SCLKH
50 – – ns – –
5.2.4 Serial Clock Low Time
t
SCLKL
50 – – ns – –
5.2.5 Enable Lead Time
(falling edge of CS
to falling
edge of SCLK)
t
leadL
200 – – ns – CLKProg = L
Enable Lead Time
(falling edge of CS
to rising
edge of SCLK)
t
leadH
200 – – ns – CLKProg = H
5.2.6 Enable Lag Time (rising edge
of SCLK to rising edge of CS
)
t
lagL
200 – – ns – CLKProg = L
Enable Lag Time (falling edge
of SCLK to rising edge of CS
)
t
lagH
200 – – ns – CLKProg = H
5.2.7 Data Setup Time (required
time SI to rising of SCLK)
t
SUL
20 – – ns – CLKProg = L
Data Setup Time (required
time SI to falling of SCLK)
t
SUH
20 – – ns – CLKProg = H
5.2.8 Data Hold Time (rising edge of
SCLK to SI)
t
HL
20 – – ns – CLKProg = L
Data Hold Time (falling edge of
SCLK to SI)
t
HH
20 – – ns – CLKProg = H
5.2.9 Disable Time
1)
t
DIS
– – 200 ns – –