D a t as h ee t , V e rs io n 2 . 7, 9 M ay 20 1 2 ® CoolSET -F3R ( J i tte r Ve r s i on ) I CE3 B0 3 65 J I CE3 B0 5 65 J I CE3 B1 5 65 J I CE3 B2 0 65 J O f f - Li ne S M P S C ur re nt Mo de C on t ro ll er w it h in t e gr at e d 6 50 V C oo lM O S ® a nd S t a rt u p c e l l (f r eq ue nc y j it t er Mo de ) in D I P - 8 Po we r M a n ag e m e n t & Su p p ly N e v e r s t o p t h i n k i n g .
CoolSET®-F3R ICE3Bxx65J Revision History: 2012-5-09 Datasheet Version 2.7 Previous Version: 2.6 Page Subjects (major changes since last revision) 23 Revised typo in outline dimension For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at http:// www.infineon.com CoolMOS ®, CoolSET® are trademarks of Infineon Technologies AG.
CoolSET®-F3R ICE3Bxx65J Off-Line SMPS Current Mode Controller with integrated 650V CoolMOS® and Startup cell (frequency jitter Mode) in DIP-8 Product Highlights • Active Burst Mode to reach the lowest Standby Power Requirements < 100mW • Adjustable Blanking Window for High Load Jumps to increase Reliability • Frequency Jittering for Low EMI • Pb-free lead plating, RoHS compilant Features Description 650V Avalanche Rugged CoolMOS ® with built in switchable Startup Cell Active Burst Mode for lowest Standby Po
CoolSET®-F3R ICE3Bxx65J Table of Contents Page 1 Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.1 Pin Configuration with PG-DIP-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.2 Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 2 Representative Blockdiagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 3 3.1 3.2 3.3 3.4 3.4.1 3.4.2 3.4.3 3.5 3.5.
CoolSET®-F3R ICE3Bxx65J 1 Pin Configuration and Functionality 1.1 Pin Configuration with PG-DIP-8 Pin Symbol Function 1 SoftS Soft-Start 2 FB Feedback 3 CS Current Sense/ 650V1) CoolMOS® Source 4 Drain 650V1) CoolMOS® Drain 5 Drain 650V1) CoolMOS® Drain 6 N.C. Not Connected 7 VCC Controller Supply Voltage 8 GND Controller Ground 1) 1.
CoolSET®-F3R ICE3Bxx65J 2 Representative Blockdiagram Figure 2 Version 2.
CoolSET®-F3R ICE3Bxx65J 3 Functional Description 3.2 All values which are used in the functional description are typical values. For calculating the worst cases the min/max values which can be found in section 4 Electrical Characteristics have to be considered. 3.1 Power Management Drain VCC Introduction Startup Cell ® CoolSET -F3 Jitter version is the further development of the CoolSET®-F2 to meet the requirements for the lowest Standby Power at minimum load and no load conditions.
CoolSET®-F3R ICE3Bxx65J When V VCC falls below the off-threshold VCCoff=10.3V the bias circuit is switched off and the Power Down reset let T1 discharging the soft-start capacitor C SoftS at pin SoftS. Thus it is ensured that at every startup cycle the voltage ramp at pin SoftS starts at zero. The bias circuit is switched off if Auto Restart Mode is entered. The current consumption is then reduced to 300uA. Once the malfunction condition is removed, this block will then turn back on.
CoolSET®-F3R ICE3Bxx65J 3.4 PWM Section 0.75 3.4.2 PWM-Latch FF1 The oscillator clock output provides a set pulse to the PWM-Latch when initiating the internal CoolMOS® conduction. After setting the PWM-Latch can be reset by the PWM comparator, the Soft Start comparator or the Current-Limit comparator. In case of resetting the driver is shut down immediately. PWM Section Oscillator Duty Cycle max 3.4.
CoolSET®-F3R ICE3Bxx65J 3.5 Current Limiting 3.5.1 Leading Edge Blanking VSense PWM Latch FF1 Vcsth tLEB = 220ns Current Limiting Propagation-Delay Compensation t Figure 9 Vcsth C10 PWM-OP Each time when the integrated internal CoolMOS® is switched on a leading edge spike is generated due to the primary-side capacitances and secondary-side rectifier reverse recovery time. This spike can cause the gate drive to switch off unintentionally.
CoolSET®-F3R ICE3Bxx65J 3.6 Current Limiting is now possible in a very accurate way. E.g. Ipeak = 0.5A with RSense = 2. Without Propagation Delay Compensation the current sense threshold is set to a static voltage level V csth=1V. A current ramp of dI/dt = 0.4A/µs, that means dV Sense/dt = 0.8V/µs, and a propagation delay time of i.e. tPropagation Delay =180ns leads then to an Ipeak overshoot of 14.4%. By means of propagation delay compensation the overshoot is only about 2% (see Figure 11).
CoolSET®-F3R ICE3Bxx65J exceeded 4.5V the switch S2 is opened and S3 is closed. The external Soft Start capacitor can now be charged further by the integrated pull up resistor R SoftS via switch S3. The comparator C3 releases the gates G5 and G6 once V Softs has exceeded 4.0V. Therefore there is no entering of Auto Restart Mode possible during this charging time of the external capacitor CSoftS.
CoolSET®-F3R ICE3Bxx65J blocks C12 by the gate G10. Maximum current can now be provided to stabilize V OUT. VFB Entering Active Burst Mode 4.5V 3.61V 3.0V 3.6.3 Protection Modes The IC provides several protection features that increase the SMPS system’s robustness and safety. The following table shows the possible system failures and the corresponding protection modes. Leaving Active Burst Mode 1.35V VSoftS t Blanking Window 4.0V 3.6V~ 3.2V 3.
CoolSET®-F3R ICE3Bxx65J small voltage overshoots of VVCC during normal operating cannot trigger the Auto Restart Mode I. In Order to ensure system reliability and prevent any false activation, a blanking time is implemented before the IC can enter into the Auto Restart Mode I. The output of the VCC overvoltage detection is fed into a spike blanking with a time constant of 8.0us. The other fault detection which can result in the Auto Restart Mode I and has this 8.
CoolSET®-F3R ICE3Bxx65J 4 Electrical Characteristics Note: All voltages are measured with respect to ground (Pin 8). The voltage levels are valid if other ratings are not violated. 4.1 Note: Absolute Maximum Ratings Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction of the integrated circuit. For the same reason make sure, that any capacitor that will be connected to pin 7 (VCC) is discharged before assembling the application circuit.
CoolSET®-F3R ICE3Bxx65J 4.2 Note: Operating Range Within the operating range the IC operates as described in the functional description. Parameter Symbol Limit Values min. max. Unit VCC Supply Voltage VVCC V VCCoff 26 V Junction Temperature of Controller TjCon -25 130 °C Junction Temperature of CoolMOS ® TJCoolMOS -25 150 °C 4.3 4.3.
CoolSET®-F3R ICE3Bxx65J 4.3.2 Internal Voltage Reference Parameter Trimmed Reference Voltage 4.3.3 Symbol VREF Limit Values min. typ. max. 4.90 5.00 5.10 Unit Test Condition V measured at pin FB IFB = 0 Unit Test Condition PWM Section Parameter Symbol Limit Values min. typ. max. fOSC3 58 67 76 kHz fOSC4 62 67 74.5 kHz Tj = 25°C Frequency Jittering Range fdelta - ±2.7 - kHz Tj = 25°C Max. Duty Cycle Dmax 0.70 0.75 0.80 Min.
CoolSET®-F3R ICE3Bxx65J Active Burst Mode Level for Comparator C6b VFBC6b 2.88 3.00 3.12 V After Active Burst Mode is entered Overvoltage Detection Limit VVCCOVP 19.5 20.5 21.5 V V FB = 5V, VSoftS = 3V TjSD 130 140 150 °C tSpike - 8.0 - ms Thermal Shutdown 1) Spike Blanking 1) The parameter is not subject to production test - verified by design/characterization Note: The trend of all the voltage levels in the Control Unit is the same regarding the deviation except VVCCOVP 4.3.
CoolSET®-F3R ICE3Bxx65J Rise Time trise - 302) - ns Fall Time tfall - 302) - ns 1) The parameter is not subject to production test - verified by design/characterization 2) Measured in a Typical Flyback Converter Application Version 2.
CoolSET®-F3R ICE3Bxx65J 5 Temperature derating curve Figure 18 Safe Operating area ( SOA ) curve for ICE3B0365J Figure 19 Safe Operating area ( SOA ) curve for ICE3B0565J Version 2.
CoolSET®-F3R ICE3Bxx65J Figure 20 Safe Operating area ( SOA ) curve for ICE3B1565J Figure 21 Safe Operating area ( SOA ) curve for ICE3B2065J Version 2.
CoolSET®-F3R ICE3Bxx65J Figure 22 Version 2.
CoolSET®-F3R ICE3Bxx65J 6 Outline Dimension PG-DIP-8 (Plastic Dual In-Line Outline) Figure 23 Version 2.
CoolSET®-F3R ICE3Bxx65J 7 Marking Marking Figure 24 Marking for ICE3B0365J Marking Figure 25 Version 2.
CoolSET®-F3R ICE3Bxx65J Marking Figure 26 Marking for ICE3B1565J Marking Figure 27 Version 2.
CoolSET®-F3R ICE3Bxx65J Schematic for recommended PCB layout 8 Schematic for recommended PCB layout Figure 28 Schematic for recommended PCB layout General guideline for PCB layout design using F3 CoolSET (refer to Figure 26): 1. “Star Ground “at bulk capacitor ground, C11: “Star Ground “means all primary DC grounds should be connected to the ground of bulk capacitor C11 separately in one point. It can reduce the switching noise going into the sensitive pins of the CoolSET device effectively.
CoolSET®-F3R ICE3Bxx65J Schematic for recommended PCB layout b. Spark Gap 1 and Spark Gap 2, Live / Neutral to GROUND: These 2 Spark Gaps can be used when the lightning surge requirement is >6KV. 230Vac input voltage application, the gap separation is around 5.5mm 115Vac input voltage application, the gap separation is around 3mm 2. Add Y-capacitor (C2 and C3) in the Live and Neutral to ground even though it is a 2-pin input 3.
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