Datasheet

ManualsBrandsINFINEON TECHNOLOGIES ManualsFETsIRF830APBF, MOSFET N channel 5A 500V

www.irf.com 1

3/20/03

IRF830A

SMPS MOSFET

HEXFET

Power MOSFET

l Switch Mode Power Supply ( SMPS )

l Uninterruptable Power Supply

l High speed power switching

Benefits

Applications

l Low Gate Charge Qg results in Simple

Drive Requirement

l Improved Gate, Avalanche and dynamic

dv/dt Ruggedness

l Fully Characterized Capacitance and

Avalanche Voltage and Current

l Effective Coss specified ( See AN 1001)

DSS

Rds(on) max I

500V 1.40Ω 5.0A

Typical SMPS Topologies:

l Two transistor Forward

l Half Bridge and Full Bridge

Parameter Max. Units

@ T

= 25°C Continuous Drain Current, V

@ 10V 5.0

@ T

= 100°C Continuous Drain Current, V

@ 10V 3.2 A

Pulsed Drain Current  20

= 25°C Power Dissipation 74 W

Linear Derating Factor 0.59 W/°C

Gate-to-Source Voltage ± 30 V

dv/dt Peak Diode Recovery dv/dt  5.3 V/ns

Operating Junction and -55 to + 150

STG

Storage Temperature Range

Soldering Temperature, for 10 seconds 300 (1.6mm from case )

°C

Mounting torqe, 6-32 or M3 screw 10 lbf•in (1.1N•m)

Absolute Maximum Ratings

TO-220AB

SDG

PD- 91878D

Notes  through  are on page 8

Summary of content (8 pages)

PAGE 1
PD- 91878D IRF830A SMPS MOSFET HEXFET® Power MOSFET Applications Switch Mode Power Supply ( SMPS ) l Uninterruptable Power Supply l High speed power switching l Benefits Low Gate Charge Qg results in Simple Drive Requirement l Improved Gate, Avalanche and dynamic dv/dt Ruggedness l Fully Characterized Capacitance and Avalanche Voltage and Current l Effective Coss specified ( See AN 1001) VDSS Rds(on) max ID 500V 1.40Ω 5.
PAGE 2
IRF830A Static @ TJ = 25°C (unless otherwise specified) Parameter Drain-to-Source Breakdown Voltage ∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient RDS(on) Static Drain-to-Source On-Resistance VGS(th) Gate Threshold Voltage V(BR)DSS IDSS Drain-to-Source Leakage Current IGSS Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Min. 500 ––– ––– 2.0 ––– ––– ––– ––– Typ. ––– 0.60 ––– ––– ––– ––– ––– ––– Max. Units Conditions ––– V VGS = 0V, ID = 250µA ––– V/°C Reference to 25°C, ID = 1mA 1.
PAGE 3
IRF830A 100 100 VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V TOP 10 I D , Drain-to-Source Current (A) I D , Drain-to-Source Current (A) TOP 1 4.5V 0.1 20µs PULSE WIDTH TJ = 25 °C 0.01 0.1 1 10 1 4.5V 20µs PULSE WIDTH TJ = 150 °C 0.1 1 100 10 100 VDS , Drain-to-Source Voltage (V) VDS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 100 2.
PAGE 4
IRF830A 20 V GS = 0V, f = 1MHz Ciss = Cgs + Cgd , Cds SHORTED Crss = Cgd Coss = Cds + C gd VGS , Gate-to-Source Voltage (V) C, Capacitance (pF) 10000 1000 Ciss 100 Coss 10 Crss 1 10 100 VDS = 400V VDS = 250V VDS = 100V 16 12 8 4 FOR TEST CIRCUIT SEE FIGURE 13 0 A 1 ID = 5.0A 0 1000 4 16 20 24 100 100 OPERATION IN THIS AREA LIMITED BY RDS(on) ID , Drain Current (A) ISD , Reverse Drain Current (A) 12 Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage Fig 5.
PAGE 5
IRF830A 5.0 RD VDS VGS ID , Drain Current (A) 4.0 D.U.T. RG 3.0 + -VDD 10V Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 % 2.0 Fig 10a. Switching Time Test Circuit 1.0 VDS 90% 0.0 25 50 75 100 125 150 TC , Case Temperature ( °C) 10% VGS Fig 9. Maximum Drain Current Vs. Case Temperature td(on) tr t d(off) tf Fig 10b. Switching Time Waveforms Thermal Response (Z thJC ) 10 1 D = 0.50 0.20 0.10 PDM 0.05 0.1 0.02 0.01 0.01 0.00001 t1 t2 SINGLE PULSE (THERMAL RESPONSE) 0.0001 Notes: 1.
PAGE 6
15V DRIVER L VDS D.U.T RG + V - DD IAS 20V 0.01Ω tp Fig 12a. Unclamped Inductive Test Circuit V(BR)DSS tp A EAS , Single Pulse Avalanche Energy (mJ) IRF830A 500 ID 2.2A 3.2A BOTTOM 5.0A TOP 400 300 200 100 0 25 50 75 100 125 150 Starting TJ , Junction Temperature( °C) I AS Fig 12c. Maximum Avalanche Energy Vs. Drain Current Fig 12b. Unclamped Inductive Waveforms QG 10 V 790 QGD VG Charge Fig 13a. Basic Gate Charge Waveform Current Regulator Same Type as D.U.T. 50KΩ 12V .
PAGE 7
IRF830A Peak Diode Recovery dv/dt Test Circuit + D.U.T Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer + - - + RG • • • • Driver Gate Drive P.W. + dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test Period D= - VDD P.W. Period VGS=10V * D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T.
PAGE 8
IRF830A Package Outline TO-220AB Outline Dimensions are shown in millimeters (inches) 2.87 (.113) 2.62 (.103) 10.54 (.415) 10.29 (.405) -B- 3.78 (.149) 3.54 (.139) 4.69 (.185) 4.20 (.165) -A- 1.32 (.052) 1.22 (.048) 6.47 (.255) 6.10 (.240) 4 15.24 (.600) 14.84 (.584) 1.15 (.045) MIN 1 2 14.09 (.555) 13.47 (.530) 4.06 (.160) 3.55 (.140) 3X 3X LEAD ASSIGNMENTS 1 - GATE 2 - DRAIN 3 - SOURCE 4 - DRAIN 3 1.40 (.055) 1.15 (.045) 0.93 (.037) 0.69 (.027) 0.36 (.014) 3X M B A M 0.55 (.022) 0.