Datasheet

ManualsBrandsINFINEON TECHNOLOGIES ManualsFETsIRL540NPBF, MOSFET N channel voltage:100V

IRL540N

HEXFET

Power MOSFET

PD - 91495A

DSS

= 100V

DS(on)

= 0.044Ω

= 36A

-22

5/13/98

Parameter Max. Units

@ T

= 25°C Continuous Drain Current, V

@ 10V 36

@ T

= 100°C Continuous Drain Current, V

@ 10V 26 A

Pulsed Drain Current  120

= 25°C Power Dissipation 140 W

Linear Derating Factor 0.91 W/°C

Gate-to-Source Voltage ± 16 V

Single Pulse Avalanche Energy 310 mJ

Avalanche Current 18 A

Repetitive Avalanche Energy 14 mJ

dv/dt Peak Diode Recovery dv/dt  5.0 V/ns

Operating Junction and -55 to + 175

STG

Storage Temperature Range

Soldering Temperature, for 10 seconds 300 (1.6mm from case )

°C

Mounting torque, 6-32 or M3 srew 10 lbf•in (1.1N•m)

Absolute Maximum Ratings

Parameter Typ. Max. Units

θJC

Junction-to-Case ––– 1.1

θCS

Case-to-Sink, Flat, Greased Surface 0.50 ––– °C/W

θJA

Junction-to-Ambient ––– 62

Thermal Resistance

Description

Fifth Generation HEXFETs from International Rectifier

utilize advanced processing techniques to achieve

extremely low on-resistance per silicon area. This

benefit, combined with the fast switching speed and

ruggedized device design that HEXFET Power

MOSFETs are well known for, provides the designer

with an extremely efficient and reliable device for use

in a wide variety of applications.

The TO-220 package is universally preferred for all

commercial-industrial applications at power dissipation

levels to approximately 50 watts. The low thermal

resistance and low package cost of the TO-220

contribute to its wide acceptance throughout the

industry.

l Logic-Level Gate Drive

l Advanced Process Technology

l Dynamic dv/dt Rating

l 175°C Operating Temperature

l Fast Switching

l Fully Avalanche Rated

Summary of content (8 pages)

PAGE 1
PD - 91495A IRL540N HEXFET® Power MOSFET l l l l l l Logic-Level Gate Drive Advanced Process Technology Dynamic dv/dt Rating 175°C Operating Temperature Fast Switching Fully Avalanche Rated D VDSS = 100V RDS(on) = 0.044Ω G ID = 36A S Description Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve extremely low on-resistance per silicon area.
PAGE 2
IRL540N Electrical Characteristics @ TJ = 25°C (unless otherwise specified) ∆V(BR)DSS/∆TJ Parameter Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Qg Qgs Qgd td(on) tr td(off) tf Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Min. 100 ––– ––– ––– ––– 1.0 14 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– Typ. ––– 0.
PAGE 3
IRL540N 1000 1000 VGS 15V 12V 10V 8.0V 6.0V 4.0V 3.0V BOTTOM 2.5V 100 10 2.5V 20µs PULSE WIDTH T J = 25°C 1 0.1 VGS 15V 12V 10V 8.0V 6.0V 4.0V 3.0V BOTTOM 2.5V TOP ID , Drain-to-Source Current (A) ID , Drain-to-Source Current (A) TOP 1 10 100 10 2.5V 20µs PULSE WIDTH T J = 175°C 1 A 100 0.1 1 V D S , Drain-to-Source Voltage (V) Fig 2. Typical Output Characteristics 3.
PAGE 4
IRL540N 3000 15 V G S , Gate-to-Source Voltage (V) V G S = 0V, f = 1MHz C iss = C gs+ C gd , C SHORTED ds C rss = C gd C oss = C ds+ C gd C, Capacitance (pF) C iss 2000 C oss 1000 C rss 0 A 1 10 I D = 18A V D S = 80V V D S = 50V V D S = 20V 12 9 6 3 FOR TEST CIRCUIT SEE FIGURE 13 0 100 0 V D S , Drain-to-Source Voltage (V) 40 60 80 A 100 Q G , Total Gate Charge (nC) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs.
PAGE 5
IRL540N 40 RD VDS I D , Drain Current (A) VGS 30 RG 20 Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 % D.U.T. + -VDD 5.0V Fig 10a. Switching Time Test Circuit 10 VDS 90% 0 25 50 75 100 125 150 175 TC , Case Temperature ( °C) 10% VGS Fig 9. Maximum Drain Current Vs. Case Temperature td(on) tr t d(off) tf Fig 10b. Switching Time Waveforms Thermal Response (Z thJC ) 10 1 D = 0.50 0.20 P DM 0.10 0.1 0.01 0.00001 0.05 0.02 0.01 t1 t2 SINGLE PULSE (THERMAL RESPONSE) Notes: 1.
PAGE 6
L VD S D .U .T RG IA S 10V tp D R IV E R + V - DD A 0.0 1 Ω Fig 12a. Unclamped Inductive Test Circuit 800 TOP BOTTOM ID 7.3A 13A 18A 600 400 200 E AS , 1 5V Single Pulse Avalanche Energy (mJ) IRL540N A 0 25 50 V (B R )D SS 75 100 125 150 Starting T J , Junction Temperature (°C) tp Fig 12c. Maximum Avalanche Energy Vs. Drain Current IAS Fig 12b. Unclamped Inductive Waveforms Current Regulator Same Type as D.U.T. 50KΩ QG 12V .2µF .3µF 5.0 V QGS D.U.T.
PAGE 7
IRL540N Peak Diode Recovery dv/dt Test Circuit + D.U.T Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer + - - + • • • • RG dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test Driver Gate Drive D= Period P.W. + - VDD P.W. Period VGS=10V D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T.
PAGE 8
IRL540N Package Outline TO-220AB Outline Dimensions are shown in millimeters (inches) 2.87 (.11 3) 2.62 (.10 3) 10 .54 (.4 15) 10 .29 (.4 05) 3 .7 8 (.149 ) 3 .5 4 (.139 ) -A - -B 4.69 ( .18 5 ) 4.20 ( .16 5 ) 1 .32 (.05 2) 1 .22 (.04 8) 6.47 (.25 5) 6.10 (.24 0) 4 1 5.24 (.60 0) 1 4.84 (.58 4) 1.15 (.04 5) M IN 1 2 1 4.09 (.55 5) 1 3.47 (.53 0) 4.06 (.16 0) 3.55 (.14 0) 3X 3X L E A D A S S IG NM E NT S 1 - GATE 2 - D R A IN 3 - S O U RC E 4 - D R A IN 3 1 .4 0 (.0 55 ) 1 .1 5 (.0 45 ) 0.