Datasheet

XMC1100
XMC1000 Family
Electrical Parameter
Data Sheet 47 V1.4, 2014-05
Figure 15 USIC - SSC Master/Slave Mode Timing
Note: This timing diagram shows a standard configuration, for which the slave select
signal is low-active, and the serial clock signal is not shifted and not inverted.
t
2
t
1
USIC_SSC_TMGX.VSD
Clock Output
SCLKOUT
Data Output
DOUT[3:0]
t
3
t
3
t
5
Data
valid
t
4
First Transmit
Edge
Data Input
DX0/DX[5:3]
Select Output
SELOx
Active
Master Mode Timing
Slave Mode Timing
t
11
t
10
Clock Input
DX1
Data Output
DOUT[3:0]
t
14
t
14
Data
valid
Data Input
DX0/DX[5:3]
Select Input
DX2
Active
t
13
t
12
Transmit Edge: with this clock edge, transmit data is shifted to transmit data output.
Receive Edge: with this clock edge, receive data at receive data input is latched.
Receive
Edge
Last Receive
Edge
InactiveInactive
Transmit
Edge
InactiveInactive
First Transmit
Edge
Receive
Edge
Transmit
Edge
Last Receive
Edge
t
5
Data
valid
t
4
Data
valid
t
12
t
13
Drawn for BRGH.SCLKCFG = 00
B
. Also valid for for SCLKCFG = 01
B
with inverted SCLKOUT signal.
Subject to Agreement on the Use of Product Information