Da ta S h e e t , V 2 .0 , J a n . 2 0 0 1 C161K C161O 16-Bit Single-Chip Microcontroller Microcontrollers N e v e r s t o p t h i n k i n g .
Edition 2001-01 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München, Germany © Infineon Technologies AG 2001. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved.
Da ta S h e e t , V 2 .0 , J a n . 2 0 0 1 C161K C161O 16-Bit Single-Chip Microcontroller Microcontrollers N e v e r s t o p t h i n k i n g .
C161K/O Revision History: 2001-01 Previous Version: 03.97 09.96 V2.0 (Preliminary) (Advance Information) Page Subjects (major changes since last revision) All Converted to Infineon layout All C161V removed 2 Ordering Codes and Cross-Reference replaced with Derivative Synopsis 5-8 Open drain functionality described for P2, P3, P6 8 Bidirectional reset introduced 19 Figure updated 28, 29 Revised description of Absolute Max.
16-Bit Single-Chip Microcontroller C166 Family C161K/O C161K/O • High Performance 16-bit CPU with 4-Stage Pipeline – 80 ns Instruction Cycle Time at 25 MHz CPU Clock – 400 ns Multiplication (16 × 16 bit), 800 ns Division (32 / 16 bit) – Enhanced Boolean Bit Manipulation Facilities – Additional Instructions to Support HLL and Operating Systems – Register-Based Design with Multiple Variable Register Banks – Single-Cycle Context Switching Support – 16 MBytes Total Linear Address Space for Code and Data – 102
C161K C161O This document describes several derivatives of the C161 group. Table 1 enumerates these derivatives and summarizes the differences. As this document refers to all of these derivatives, some descriptions may not apply to a specific product. Table 1 C161K/O Derivative Synopsis Derivative1) Max. Oper. Frequency Operating Voltage IRAM Nr of Ext. [KB] CSs Intr. CAP IN SAF-C161K-LM 20 MHz 4.5 to 5.5 V 1 2 4 --- SAB-C161K-LM 20 MHz 4.5 to 5.5 V 1 2 4 --- SAF-C161K-L25M 25 MHz 4.
C161K C161O Introduction The C161K/O is a derivative of the Infineon C166 Family of full featured single-chip CMOS microcontrollers. It combines high CPU performance (up to 12.5 million instructions per second) with peripheral functionality and enhanced IO-capabilities. The C161K/O is especially suited for cost sensitive applications.
C161K C161O P1H.7/A15 P1H.6/A14 VDD VSS 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 P5.15/T2EUD P5.14/T4EUD P2.15/EX7IN P2.14/EX6IN P2.13/EX5IN P2.12/EX4IN P2.11/EX3IN P2.10/EX2IN P2.9/EX1IN P6.3/CS3 P6.2/CS2 P6.1/CS1 P6.0/CS0 NMI RSTOUT RSTIN Pin Configuration MQFP Package (top view) VSS XTAL1 XTAL2 VDD 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 C161K/O P1H.5/A13 P1H.4/A12 P1H.3/A11 P1H.2/A10 P1H.1/A9 P1H.0/A8 P1L.7/A7 P1L.6/A6 P1L.5/A5 P1L.4/A4 P1L.3/A3 P1L.
C161K C161O Table 2 Pin Definitions and Functions Symbol Pin Num Input Outp. Function XTAL1 2 I XTAL1: XTAL2 3 O P3 Input to the oscillator amplifier and input to the internal clock generator XTAL2: Output of the oscillator amplifier circuit. To clock the device from an external source, drive XTAL1, while leaving XTAL2 unconnected. Minimum and maximum high/low and rise/fall times specified in the AC Characteristics must be observed. IO Port 3 is a 12-bit bidirectional I/O port.
C161K C161O Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Num Input Outp. Function RD 25 O External Memory Read Strobe. RD is activated for every external instruction or data read access. WR/ WRL 26 O External Memory Write Strobe. In WR-mode this pin is activated for every external data write access. In WRL-mode this pin is activated for low byte data write accesses on a 16bit bus, and for every data write access on an 8-bit bus. See WRCFG in register SYSCON for mode selection.
C161K C161O Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Num Input Outp. Function RSTIN I/O Reset Input with Schmitt-Trigger characteristics. A low level at this pin while the oscillator is running resets the C161K/O. An internal pullup resistor permits power-on reset using only a capacitor connected to VSS. A spike filter suppresses input pulses < 10 ns. Input pulses >100 ns safely pass the filter. The minimum duration for a safe recognition should be 100 ns + 2 CPU clock cycles.
C161K C161O Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Num Input Outp. Function P2 IO Port 2 is a 7-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 2 outputs can be configured as push/ pull or open drain drivers.
C161K C161O Functional Description The architecture of the C161K/O combines advantages of both RISC and CISC processors and of advanced peripheral subsystems in a very well-balanced way. In addition the on-chip memory blocks allow the design of compact systems with maximum performance. The following block diagram gives an overview of the different on-chip components and of the advanced, high bandwidth internal bus structure of the C161K/O.
C161K C161O Memory Organization The memory space of the C161K/O is configured in a Von Neumann architecture which means that code memory, data memory, registers and I/O ports are organized within the same linear address space which includes 16 MBytes. The entire memory space can be accessed bytewise or wordwise. Particular portions of the on-chip memory have additionally been made directly bitaddressable.
C161K C161O External Bus Controller All of the external memory accesses are performed by a particular on-chip External Bus Controller (EBC).
C161K C161O Central Processing Unit (CPU) The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a separate multiply and divide unit, a bit-mask generator and a barrel shifter. Based on these hardware provisions, most of the C161K/O’s instructions can be executed in just one machine cycle which requires 80 ns at 25 MHz CPU clock.
C161K C161O The CPU has a register context consisting of up to 16 wordwide GPRs at its disposal. These 16 GPRs are physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the base address of the active register bank to be accessed by the CPU at any time. The number of register banks is only restricted by the available internal RAM space. For easy parameter passing, a register bank may overlap others.
C161K C161O Interrupt System With an interrupt response time within a range from just 5 to 12 CPU clocks (in case of internal program execution), the C161K/O is capable of reacting very fast to the occurrence of non-deterministic events. The architecture of the C161K/O supports several mechanisms for fast and flexible response to service requests that can be generated from various sources internal or external to the microcontroller.
C161K C161O Table 3 C161K/O Interrupt Nodes Source of Interrupt or Request PEC Service Request Flag Enable Flag Interrupt Vector Vector Location Trap Number External Interrupt 1 CC9IR CC9IE CC9INT 00’0064H 19H External Interrupt 2 CC10IR CC10IE CC10INT 00’0068H 1AH External Interrupt 3 CC11IR CC11IE CC11INT 00’006CH 1BH External Interrupt 4 CC12IR CC12IE CC12INT 00’0070H 1CH External Interrupt 5 CC13IR CC13IE CC13INT 00’0074H 1DH External Interrupt 6 CC14IR CC14IE CC
C161K C161O The C161K/O also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware traps cause immediate non-maskable system reaction which is similar to a standard interrupt service (branching to a dedicated vector table location). The occurrence of a hardware trap is additionally signified by an individual bit in the trap flag register (TFR).
C161K C161O General Purpose Timer (GPT) Unit The GPT unit represents a very flexible multifunctional timer/counter structure which may be used for many different time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. The GPT unit incorporates five 16-bit timers which are organized in two separate modules, GPT1 and GPT2.
C161K C161O U/D T2EUD fCPU 2n : 1 T2IN Interrupt Request GPT1 Timer T2 T2 Mode Control Reload Capture fCPU Interrupt Request n 2 :1 Toggle FF T3 Mode Control T3IN GPT1 Timer T3 T3OTL T3OUT U/D T3EUD Other Timers Capture Reload T4IN fCPU 2n : 1 T4 Mode Control GPT1 Timer T4 Interrupt Request U/D T4EUD MCT02141 n = 3 … 10 Figure 5 Block Diagram of GPT1 With its maximum resolution of 8 TCL, the GPT2 module provides precise event control and time measurement.
C161K C161O The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of GPT1 timer T3’s inputs T3IN and/or T3EUD. This is especially advantageous when T3 operates in Incremental Interface Mode. Note: Block GPT2 is only available in the C161O, not in the C161K.
C161K C161O Serial Channels Serial communication with other microcontrollers, processors, terminals or external peripheral components is provided by two serial interfaces with different functionality, an Asynchronous/Synchronous Serial Channel (ASC0) and a High-Speed Synchronous Serial Channel (SSC).
C161K C161O Watchdog Timer The Watchdog Timer represents one of the fail-safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time. The Watchdog Timer is always enabled after a reset of the chip, and can only be disabled in the time interval until the EINIT (end of initialization) instruction has been executed. Thus, the chip’s start-up procedure is always monitored. The software has to be designed to service the Watchdog Timer before it overflows.
C161K C161O Instruction Set Summary Table 5 lists the instructions of the C161K/O in a condensed way. The various addressing modes that can be used with a specific instruction, the operation of the instructions, parameters for conditional execution of instructions, and the opcodes for each instruction can be found in the “C166 Family Instruction Set Manual”. This document also provides a detailed description of each instruction.
C161K C161O Table 5 Instruction Set Summary (cont’d) Mnemonic MOV(B) MOVBS MOVBZ JMPA, JMPI, JMPR JMPS J(N)B JBC JNBS CALLA, CALLI, CALLR CALLS PCALL TRAP PUSH, POP SCXT RET RETS RETP RETI SRST IDLE PWRDN SRVWDT DISWDT EINIT ATOMIC EXTR EXTP(R) EXTS(R) NOP Data Sheet Description Move word (byte) data Move byte operand to word operand with sign extension Move byte operand to word operand.
C161K C161O Special Function Registers Overview The following table lists all SFRs which are implemented in the C161K/O in alphabetical order. Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the Extended SFR-Space (ESFRs) are marked with the letter “E” in column “Physical Address”. Registers within on-chip X-peripherals are marked with the letter “X” in column “Physical Address”. An SFR can be specified via its individual mnemonic name.
C161K C161O Table 6 Name C161K/O Registers, Ordered by Name (cont’d) Physical Address 8-Bit Description Addr.
C161K C161O Table 6 Name C161K/O Registers, Ordered by Name (cont’d) Physical Address 8-Bit Description Addr.
C161K C161O Table 6 Name C161K/O Registers, Ordered by Name (cont’d) Physical Address 8-Bit Description Addr.
C161K C161O Absolute Maximum Ratings Table 7 Absolute Maximum Rating Parameters Parameter Symbol Limit Values Unit Notes min. max. TST TJ VDD -65 150 °C – -40 150 °C under bias -0.5 6.5 V – Voltage on any pin with respect to ground (VSS) VIN -0.5 VDD + 0.5 V – Input current on any pin during overload condition – -10 10 mA – Absolute sum of all input currents during overload condition – – |100| mA – Power dissipation PDISS – 1.
C161K C161O Operating Conditions The following operating conditions must not be exceeded in order to ensure correct operation of the C161K/O. All parameters specified in the following sections refer to these operating conditions, unless otherwise noticed. Table 8 Operating Condition Parameters Parameter Symbol Standard digital supply voltage (5 V versions) VDD Reduced digital supply voltage (3 V versions) VDD VSS IOV Overload current Absolute sum of overload Σ|IOV| Limit Values Unit Notes min.
C161K C161O Parameter Interpretation The parameters listed in the following partly represent the characteristics of the C161K/ O and partly its demands on the system. To aid in interpreting the parameters right, when evaluating them for a design, they are marked in column “Symbol”: CC (Controller Characteristics): The logic of the C161K/O will provide signals with the respective timing characteristics.
C161K C161O DC Characteristics (Standard Supply Voltage Range) (cont’d) (Operating Conditions apply)1) Parameter Symbol 4) RSTIN active current RD/WR inact. current7) RD/WR active current7) ALE inactive current7) ALE active current7) Port 6 inactive current7) Port 6 active current7) PORT0 configuration current7) XTAL1 input current Pin capacitance8) (digital inputs/outputs) 6) IRSTL IRWH5) IRWL6) IALEL5) IALEH6) IP6H5) IP6L6) IP0H5) IP0L6) IIL CC CIO CC Limit Values Unit Test Condition min. max.
C161K C161O DC Characteristics (Reduced Supply Voltage Range) (Operating Conditions apply)1) Parameter Symbol Limit Values min. Input low voltage (TTL, all except XTAL1) VIL Input low voltage XTAL1 VIL2 SR -0.5 VIH SR 1.8 Input high voltage (TTL, all except RSTIN and XTAL1) SR -0.5 Unit Test Condition max. 0.8 V – 0.3 VDD V – VDD + V – V – V – 0.5 Input high voltage RSTIN (when operated as input) VIH1 SR 0.6 VDD VDD + Input high voltage XTAL1 VIH2 SR 0.7 VDD VDD + 0.5 0.
C161K C161O DC Characteristics (Reduced Supply Voltage Range) (cont’d) (Operating Conditions apply)1) Parameter PORT0 configuration current Symbol 7) XTAL1 input current Pin capacitance8) (digital inputs/outputs) 5) IP0H IP0L6) IIL CC CIO CC Limit Values Unit Test Condition min. max.
C161K C161O Power Consumption C161K/O (Standard Supply Voltage Range) (Operating Conditions apply) Parameter Symbol Limit Values min. max. Unit Test Condition Power supply current (active) with all peripherals active IDD5 – 15 + mA 1.8 × fCPU RSTIN = VIL fCPU in [MHz]1) Idle mode supply current with all peripherals active IIDX5 – 2+ mA 0.
C161K C161O I mA 100 IDD5max 80 IDD5typ IDD3max 60 IDD3typ 40 IIDX5max IIDX3max IIDX5typ IIDX3typ 20 0 0 10 20 30 40 MHz fCPU MCD04860 Figure 7 Data Sheet Supply/Idle Current as a Function of Operating Frequency 35 V2.
C161K C161O AC Characteristics Definition of Internal Timing The internal operation of the C161K/O is controlled by the internal CPU clock fCPU. Both edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles) operations. The specification of the external timing (AC Characteristics) therefore depends on the time between two consecutive edges of the CPU clock, called “TCL” (see Figure 8).
C161K C161O Table 9 CLKCFG (P0H.7-5) 0 X X 1 X X 1) C161K/O Clock Generation Modes CPU Frequency External Clock fCPU = fOSC × F Input Range Notes fOSC × 1 fOSC / 2 1 to 25 MHz Direct drive1) 2 to 50 MHz CPU clock via prescaler The maximum frequency depends on the duty cycle of the external clock signal. Prescaler Operation When prescaler operation is configured (CLKCFG = 1XXB) the CPU clock is derived from the internal oscillator (input clock signal) by a 2:1 prescaler.
C161K C161O AC Characteristics Table 10 External Clock Drive XTAL1 (Standard Supply Voltage Range) (Operating Conditions apply) Parameter Symbol Direct Drive 1:1 min. Oscillator period tOSC SR 40 1) High time Low time1) Rise time1) Fall time1) t1 t2 t3 t4 Prescaler 2:1 max. min. max. Unit – 20 – ns 2) – 6 – ns SR 202) – 6 – ns SR – 10 – 6 ns SR – 10 – 6 ns SR 20 1) The clock input signal must reach the defined levels VIL2 and VIH2.
C161K C161O t1 t3 t4 VIH2 0.5 VDD VIL t2 t OSC MCT02534 Figure 9 External Clock Drive XTAL1 Note: If the on-chip oscillator is used together with a crystal, the oscillator frequency is limited to a range of 4 MHz to 40 MHz. It is strongly recommended to measure the oscillation allowance (or margin) in the final target system (layout) to determine the optimum parameters for the oscillator operation. Please refer to the limits specified by the crystal supplier.
C161K C161O Testing Waveforms 2.4 V 1.8 V 1.8 V Test Points 0.8 V 0.8 V ’ 0.45 V ’ ’ AC inputs during testing are driven at 2.4 V for a logic 1’ and 0.45 V for a logic 0’. Timing measurements are made at VIH min for a logic 1’ and VIL max for a logic 0’. ’ MCA04414 Figure 10 Input Output Waveforms VLoad + 0.1 V VOH - 0.1 V Timing Reference Points VLoad - 0.1 V VOL + 0.
C161K C161O Memory Cycle Variables The timing tables below use three variables which are derived from the BUSCONx registers and represent the special characteristics of the programmed memory cycle. The following table describes, how these variables are to be computed.
C161K C161O Multiplexed Bus (Standard Supply Voltage Range) (cont’d) (Operating Conditions apply) ALE cycle time = 6 TCL + 2tA + tC + tF (120 ns at 25 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 25 MHz 1 / 2TCL = 1 to 25 MHz min. max. min. max.
C161K C161O Multiplexed Bus (Standard Supply Voltage Range) (cont’d) (Operating Conditions apply) ALE cycle time = 6 TCL + 2tA + tC + tF (120 ns at 25 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 25 MHz 1 / 2TCL = 1 to 25 MHz min. max. min. max.
C161K C161O AC Characteristics Multiplexed Bus (Reduced Supply Voltage Range) (Operating Conditions apply) ALE cycle time = 6 TCL + 2tA + tC + tF (150 ns at 20 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 20 MHz 1 / 2TCL = 1 to 20 MHz min. max. min. max.
C161K C161O Multiplexed Bus (Reduced Supply Voltage Range) (cont’d) (Operating Conditions apply) ALE cycle time = 6 TCL + 2tA + tC + tF (150 ns at 20 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 20 MHz 1 / 2TCL = 1 to 20 MHz min. max. min. max.
C161K C161O Multiplexed Bus (Reduced Supply Voltage Range) (cont’d) (Operating Conditions apply) ALE cycle time = 6 TCL + 2tA + tC + tF (150 ns at 20 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 20 MHz 1 / 2TCL = 1 to 20 MHz min. max. min. max.
C161K C161O t5 t16 t25 ALE t38 t39 t40 CSxL t17 t27 A21-A16 (A15-A8) BHE, CSxE Address t54 t19 t6 t7 t18 Read Cycle BUS Address t8 Data IN t10 t14 t12 RD t42 ` t44 t51 t52 t46 t48 RdCSx t23 Write Cycle BUS Address t8 Data OUT t10 t22 t56 t12 WR, WRL, WRH t42 t44 t50 WrCSx t48 MCT04861 Figure 12 Data Sheet External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Normal ALE 47 V2.
C161K C161O t5 t16 t25 ALE t38 t39 t40 CSxL t17 A21-A16 (A15-A8) BHE, CSxE t27 Address t6 t54 t19 t7 t18 Read Cycle BUS Address Data IN t8 t10 t14 t12 RD t42 t4 t51 t52 t46 t48 RdCSx t23 Write Cycle BUS Address Data OUT t8 t10 t22 t56 t12 WR, WRL, WRH t42 t44 t50 t48 WrCSx MCT04862 Figure 13 External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Extended ALE Data Sheet 48 V2.
C161K C161O t5 t16 t25 ALE t38 t39 t40 CSxL t17 t27 A21-A16 (A15-A8) BHE, CSxE Address t54 t19 t6 t7 t18 Read Cycle BUS Address t9 Data IN t11 t15 t13 RD t43 t45 t51 t52 t47 t49 RdCSx t23 Write Cycle BUS Address t9 Data OUT t11 t22 t56 t13 WR, WRL, WRH t43 t45 t50 t49 WrCSx MCT04863 Figure 14 Data Sheet External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Normal ALE 49 V2.
C161K C161O t5 t16 t25 ALE t38 t39 t40 CSxL t17 A21-A16 (A15-A8) BHE, CSxE t27 Address t6 t54 t19 t7 t18 Read Cycle BUS Address Data IN t9 t11 t15 t13 RD t43 t45 t51 t47 t49 t52 RdCSx t23 Write Cycle BUS Address Data OUT t9 t11 t22 t56 t13 WR, WRL, WRH t43 t45 t50 t49 WrCSx MCT04864 Figure 15 Data Sheet External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Extended ALE 50 V2.
C161K C161O AC Characteristics Demultiplexed Bus (Standard Supply Voltage Range) (Operating Conditions apply) ALE cycle time = 4 TCL + 2tA + tC + tF (80 ns at 25 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock = 25 MHz min. Variable CPU Clock Unit 1 / 2TCL = 1 to 25 MHz max. min. max.
C161K C161O Demultiplexed Bus (Standard Supply Voltage Range) (cont’d) (Operating Conditions apply) ALE cycle time = 4 TCL + 2tA + tC + tF (80 ns at 25 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock = 25 MHz min. Variable CPU Clock Unit 1 / 2TCL = 1 to 25 MHz max. min. max.
C161K C161O Demultiplexed Bus (Standard Supply Voltage Range) (cont’d) (Operating Conditions apply) ALE cycle time = 4 TCL + 2tA + tC + tF (80 ns at 25 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock = 25 MHz min. Data float after RdCS (with RW-delay)1) t53 SR – Variable CPU Clock Unit 1 / 2TCL = 1 to 25 MHz max. min. max.
C161K C161O AC Characteristics Demultiplexed Bus (Reduced Supply Voltage Range) (Operating Conditions apply) ALE cycle time = 4 TCL + 2tA + tC + tF (100 ns at 20 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock = 20 MHz min. Variable CPU Clock Unit 1 / 2TCL = 1 to 20 MHz max. min. max.
C161K C161O Demultiplexed Bus (Reduced Supply Voltage Range) (cont’d) (Operating Conditions apply) ALE cycle time = 4 TCL + 2tA + tC + tF (100 ns at 20 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock = 20 MHz min. Variable CPU Clock Unit 1 / 2TCL = 1 to 20 MHz max. min. max.
C161K C161O Demultiplexed Bus (Reduced Supply Voltage Range) (cont’d) (Operating Conditions apply) ALE cycle time = 4 TCL + 2tA + tC + tF (100 ns at 20 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock = 20 MHz min. Data float after RdCS (with RW-delay)1) t53 SR – Variable CPU Clock Unit 1 / 2TCL = 1 to 20 MHz max. min. max.
C161K C161O t5 t16 t26 ALE t38 t39 t41 CSxL t28 t17 A21-A16 A15-A0 BHE, CSxE Address t55 t6 t20 Read Cycle BUS (D15-D8) D7-D0 t18 Data IN t8 t14 t12 t42 t46 t48 RD t51 t53 RdCSx Write Cycle BUS (D15-D8) D7-D0 t24 Data OUT t8 t22 t57 t12 WR, WRL, WRH t42 t50 t48 WrCSx MCT04865 Figure 16 Data Sheet External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Normal ALE 57 V2.
C161K C161O t5 t16 t26 ALE t38 t39 t41 CSxL t17 A21-A16 A15-A0 BHE, CSxE t28 Address t6 t55 t20 Read Cycle BUS (D15-D8) D7-D0 t18 Data IN t8 t14 t12 t42 t46 t48 RD t51 t53 RdCSx Write Cycle BUS (D15-D8) D7-D0 t24 Data OUT t8 t22 t57 t12 WR, WRL, WRH t42 t50 t48 WrCSx MCT04866 Figure 17 Data Sheet External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Extended ALE 58 V2.
C161K C161O t5 t16 t26 ALE t38 t39 t41 CSxL t28 t17 A21-A16 A15-A0 BHE, CSxE Address t55 t6 t21 Read Cycle BUS (D15-D8) D7-D0 t18 Data IN t9 t15 t13 t43 t47 t49 RD t51 t68 RdCSx Write Cycle t24 BUS (D15-D8) D7-D0 Data OUT t22 t9 t57 t13 WR, WRL, WRH t43 t50 t49 WrCSx MCT04867 Figure 18 External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Normal ALE Data Sheet 59 V2.
C161K C161O t5 t16 t26 ALE t38 t39 t41 CSxL t17 A21-A16 A15-A0 BHE, CSxE t28 Address t6 t55 t21 Read Cycle BUS (D15-D8) D7-D0 t18 Data IN t9 t15 t13 t43 t47 t49 RD t51 t68 RdCSx Write Cycle BUS (D15-D8) D7-D0 t24 Data OUT t9 t22 t57 t13 WR, WRL, WRH t43 t50 t49 WrCSx MCT04868 Figure 19 Data Sheet External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Extended ALE 60 V2.
C161K C161O Package Outlines H 0.65 7˚max 0.15 +0.08 -0.02 0.25 min 2 +0.1 -0.05 2.45 max P-MQFP-80-1 (SMD) (Plastic Metric Quad Flat Package) 0.88 0.3 ±0.08 C 0.1 12.35 0.12 17.2 0.2 A-B D 80x 0.2 A-B D H 4x 14 1) M A-B D C 80x D B 14 1) 17.2 A 80 1 Index Marking 0.6x45˚ GPR05249 1) Does not include plastic or metal protrusions of 0.25 max per side Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”.
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