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C161PI Revision History: Previous Versions: 1999-07 Preliminary 1998-05 1998-01 1997-12 (C161RI / Preliminary) (C161RI / Advance Information) (C161RI / Advance Information) Page Subjects --- 3 V specification introduced 4, 5, 7 Signal FOUT added 14 XRAM description added 15 Unlatched CS description added 23 Block Diagram corrected 24 Description of divider chain improved 25, 51, 52 ADC description updated to 10-bit 36, 37 Revised description of Absolute Max.
C166 Family of High-Performance CMOS 16-Bit Microcontrollers C161PI Preliminary C161PI 16-Bit Microcontroller • High Performance 16-bit CPU with 4-Stage Pipeline – 80 ns Instruction Cycle Time at 25 MHz CPU Clock – 400 ns Multiplication (16 × 16 bit), 800 ns Division (32 / 16 bit) – Enhanced Boolean Bit Manipulation Facilities – Additional Instructions to Support HLL and Operating Systems – Register-Based Design with Multiple Variable Register Banks – Single-Cycle Context Switching Support – 16 MBytes Tot
& 3, This document describes the SAB-C161PI-LM, the SAB-C161PI-LF, the SAF-C161PILM and the SAF-C161PI-LF. For simplicity all versions are referred to by the term C161PI throughout this document. Ordering Information The ordering code for Infineon microcontrollers provides an exact reference to the required product. This ordering code identifies: • • • • the derivative itself, i.e. its function set the specified temperature range the package the type of delivery.
& 3, Introduction The C161PI is a derivative of the Infineon C166 Family of 16-bit single-chip CMOS microcontrollers. It combines high CPU performance (up to 8 million instructions per second) with high peripheral functionality and enhanced IO-capabilities. The C161PI derivative is especially suited for cost sensitive applications.
& 3, 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 P5.1/AN1 P5.0/AN0 VAGND VAREF P2.15/EX7IN P2.14/EX6IN P2.13/EX5IN P2.12/EX4IN P2.11/EX3IN P2.10/EX2IN P2.9/EX1IN P2.8/EX0IN P6.7/SDA2 P6.6/SCL1 P6.5/SDA1 P6.4/CS4 P6.3/CS3 P6.2/CS2 P6.1/CS1 P6.
& 3, 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 P5.3/AN3 P5.2/AN2 P5.1/AN1 P5.0/AN0 VAGND VAREF P2.15/EX7IN P2.14/EX6IN P2.13/EX5IN P2.12/EX4IN P2.11/EX3IN P2.10/EX2IN P2.9/EX1IN P2.8/EX0IN P6.7/SDA2 P6.6/SCL1 P6.5/SDA1 P6.4/CS4 P6.3/CS3 P6.2/CS2 P6.1/CS1 P6.
& 3, Table 1 Pin Definitions and Functions Symbol Pin Pin Input Function Num. Num. Outp. TQFP MQFP P5 I P5.0 P5.1 P5.2 P5.3 P5.14 P5.15 97 98 99 100 1 2 99 100 1 2 3 4 I I I I I I Port 5 is a 6-bit input-only port with Schmitt-Trigger characteristics. The pins of Port 5 also serve as (up to 4) analog input channels for the A/D converter, or they serve as timer inputs: AN0 AN1 AN2 AN3 T4EUD GPT1 Timer T4 Ext. Up/Down Ctrl. Input T2EUD GPT1 Timer T5 Ext. Up/Down Ctrl.
& 3, Table 1 Pin Definitions and Functions (continued) Symbol Pin Pin Input Function Num. Num. Outp. TQFP MQFP P3 IO P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 7 8 9 10 11 12 9 10 11 12 13 14 I/O I/O I O I I P3.6 P3.7 13 14 15 16 I I P3.8 P3.9 P3.10 P3.11 P3.12 15 16 17 18 19 17 18 19 20 21 P3.13 P3.15 20 21 22 23 I/O I/O O I/O O O I/O O O Port 3 is a 15-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits.
& 3, Table 1 Pin Definitions and Functions (continued) Symbol Pin Pin Input Function Num. Num. Outp. TQFP MQFP P4 IO Port 4 is a 7-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. Port 4 outputs can be configured as push/pull or open drain drivers. The input threshold of Port 4 is selectable (TTL or special).
& 3, Table 1 Pin Definitions and Functions (continued) Symbol Pin Pin Input Function Num. Num. Outp. TQFP MQFP EA 35 PORT0 P0L.0-7 3845 P0H.0-7 4855 PORT1 P1L.0-7 5663 P1H.0-7 6673 Data Sheet 37 I External Access Enable pin. A low level at this pin during and after Reset forces the C161PI to begin instruction execution out of external memory. A high level forces execution out of the internal program memory. "ROMless" versions must have this pin tied to ‘0’.
& 3, Table 1 Pin Definitions and Functions (continued) Symbol Pin Pin Input Function Num. Num. Outp. TQFP MQFP RSTIN 76 78 I/O Reset Input with Schmitt-Trigger characteristics. A low level at this pin while the oscillator is running resets the C161PI. An internal pullup resistor permits power-on reset using only a capacitor connected to 9SS. A spike filter suppresses input pulses <10 ns. Input pulses >100 ns safely pass the filter.
& 3, Table 1 Pin Definitions and Functions (continued) Symbol Pin Pin Input Function Num. Num. Outp. TQFP MQFP P6 P6.0 P6.1 P6.2 P6.3 P6.4 P6.5 P6.6 P6.7 IO 79 80 81 82 83 84 85 86 81 82 83 84 85 86 87 88 O O O O O I/O I/O I/O Port 6 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. Port 6 outputs can be configured as push/pull or open drain drivers.
& 3, Table 1 Pin Definitions and Functions (continued) Symbol Pin Pin Input Function Num. Num. Outp. TQFP MQFP 9DD 6, 23, 37, 47, 65, 75 8, 25, 39, 49, 67, 77 Digital Supply Voltage: + 5 V or + 3 V during normal operation and idle mode. ≥ 2.5 V during power down mode 9SS 3, 22, 36, 46, 64, 74 5, 24, 38, 48, 66, 76 Digital Ground.
& 3, Functional Description The architecture of the C161PI combines advantages of both RISC and CISC processors and of advanced peripheral subsystems in a very well-balanced way. The following block diagram gives an overview of the different on-chip components and of the advanced, high bandwidth internal bus structure of the C161PI. & &RUH (no internal ROM) 32 16 Data &38 &RUH &38 Instr.
& 3, Memory Organization The memory space of the C161PI is configured in a Von Neumann architecture which means that code memory, data memory, registers and I/O ports are organized within the same linear address space which includes 16 MBytes. The entire memory space can be accessed bytewise or wordwise. Particular portions of the on-chip memory have additionally been made directly bitaddressable.
& 3, External Bus Controller All of the external memory accesses are performed by a particular on-chip External Bus Controller (EBC).
& 3, Central Processing Unit (CPU) The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a separate multiply and divide unit, a bit-mask generator and a barrel shifter. Based on these hardware provisions, most of the C161PI’s instructions can be executed in just one machine cycle which requires 2 CPU clocks (4 TCL).
& 3, The CPU has a register context consisting of up to 16 wordwide GPRs at its disposal. These 16 GPRs are physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the base address of the active register bank to be accessed by the CPU at any time. The number of register banks is only restricted by the available internal RAM space. For easy parameter passing, a register bank may overlap others.
& 3, Interrupt System With an interrupt response time within a range from just 5 to 12 CPU clocks (in case of internal program execution), the C161PI is capable of reacting very fast to the occurrence of non-deterministic events. The architecture of the C161PI supports several mechanisms for fast and flexible response to service requests that can be generated from various sources internal or external to the microcontroller.
& 3, Table 2 C161PI Interrupt Nodes Source of Interrupt or Request PEC Service Request Flag Enable Flag Interrupt Vector Vector Location Trap Number External Interrupt 0 CC8IR CC8IE CC8INT 00’0060H 18H External Interrupt 1 CC9IR CC9IE CC9INT 00’0064H 19H External Interrupt 2 CC10IR CC10IE CC10INT 00’0068H 1AH External Interrupt 3 CC11IR CC11IE CC11INT 00’006CH 1BH External Interrupt 4 CC12IR CC12IE CC12INT 00’0070H 1CH External Interrupt 5 CC13IR CC13IE CC13INT 0
& 3, The C161PI also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware traps cause immediate non-maskable system reaction which is similar to a standard interrupt service (branching to a dedicated vector table location). The occurence of a hardware trap is additionally signified by an individual bit in the trap flag register (TFR).
& 3, General Purpose Timer (GPT) Unit The GPT unit represents a very flexible multifunctional timer/counter structure which may be used for many different time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. The GPT unit incorporates five 16-bit timers which are organized in two separate modules, GPT1 and GPT2.
& 3, T2EUD fCPU U/D 2n : 1 T2IN fCPU Interrupt Request GPT1 Timer T2 T2 Mode Control Reload Capture Interrupt Request 2n : 1 Toggle FF T3 Mode Control T3IN GPT1 Timer T3 T3OTL T3OUT U/D T3EUD Other Timers Capture Reload T4IN fCPU 2n : 1 T4 Mode Control GPT1 Timer T4 U/D T4EUD Figure 6 Interrupt Request MCT02141 Block Diagram of GPT1 With its maximum resolution of 8 TCL, the GPT2 module provides precise event control and time measurement.
& 3, The state of this latch may be used to clock timer T5. The overflows/underflows of timer T6 can additionally be used to cause a reload from the CAPREL register. The CAPREL register may capture the contents of timer T5 based on an external signal transition on the corresponding port pin (CAPIN), and timer T5 may optionally be cleared after the capture procedure. This allows absolute time differences to be measured or pulse multiplication to be performed without software overhead.
& 3, Real Time Clock The Real Time Clock (RTC) module of the C161PI consists of a chain of 3 divider blocks, a fixed 8:1 divider, the reloadable 16-bit timer T14, and the 32-bit RTC timer (accessible via registers RTCH and RTCL). The RTC module is directly clocked with the on-chip oscillator frequency divided by 32 via a separate clock driver (IRTC = IOSC / 32) and is therefore independent from the selected clock generation mode of the C161PI. All timers count up.
& 3, A/D Converter For analog signal measurement, a 10-bit A/D converter with 4 multiplexed input channels and a sample and hold circuit has been integrated on-chip. It uses the method of successive approximation. The sample time (for loading the capacitors) and the conversion time is programmable and can so be adjusted to the external circuitry.
& 3, Serial Channels Serial communication with other microcontrollers, processors, terminals or external peripheral components is provided by two serial interfaces with different functionality, an Asynchronous/Synchronous Serial Channel (ASC0) and a High-Speed Synchronous Serial Channel (SSC).
& 3, I2C Module The integrated I2C Bus Module handles the transmission and reception of frames over the two-line I2C bus in accordance with the I2C Bus specification. The on-chip I2C Module can receive and transmit data using 7-bit or 10-bit addressing and it can operate in slave mode, in master mode or in multi-master mode. Several physical interfaces (port pins) can be established under software control. Data can be transferred at speeds up to 400 Kbit/sec.
& 3, Parallel Ports The C161PI provides up to 76 IO lines which are organized into six input/output ports and one input port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O ports are true bidirectional ports which are switched to high impedance state when configured as inputs.
& 3, Instruction Set Summary The table below lists the instructions of the C161PI in a condensed way. The various addressing modes that can be used with a specific instruction, the operation of the instructions, parameters for conditional execution of instructions, and the opcodes for each instruction can be found in the “C166 Family Instruction Set Manual”. This document also provides a detailled description of each instruction.
& 3, Table 4 Instruction Set Summary (continued) Mnemonic MOV(B) MOVBS MOVBZ JMPA, JMPI, JMPR JMPS J(N)B JBC JNBS CALLA, CALLI, CALLR CALLS PCALL TRAP PUSH, POP SCXT RET RETS RETP RETI SRST IDLE PWRDN SRVWDT DISWDT EINIT ATOMIC EXTR EXTP(R) EXTS(R) NOP Data Sheet Description Move word (byte) data Move byte operand to word operand with sign extension Move byte operand to word operand.
& 3, Special Function Registers Overview The following table lists all SFRs which are implemented in the C161PI in alphabetical order. Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the Extended SFR-Space (ESFRs) are marked with the letter “E” in column “Physical Address”. Registers within on-chip X-Peripherals (I²C) are marked with the letter “X” in column “Physical Address”. An SFR can be specified via its individual mnemonic name.
& 3, Table 5 Name C161PI Registers, Ordered by Name (continued) Physical Address 8-Bit Description Addr. Reset Value CC12IC b FF90H C8H External Interrupt 4 Control Register 0000H CC13IC b FF92H C9H External Interrupt 5 Control Register 0000H CC14IC b FF94H CAH External Interrupt 6 Control Register 0000H CC15IC b FF96H CBH External Interrupt 7 Control Register 0000H FE10H 08H CPU Context Pointer Register FC00H b FF6AH B5H GPT2 CAPREL Interrupt Ctrl.
& 3, Table 5 C161PI Registers, Ordered by Name (continued) Name Physical Address IDPROG F078H E 3CH Identifier 0000H ISNC b F1DEH E EFH Interrupt Subnode Control Register 0000H MDC b FF0EH 87H CPU Multiply Divide Control Register 0000H MDH FE0CH 06H CPU Multiply Divide Reg. – High Word 0000H MDL FE0EH 07H CPU Multiply Divide Reg.
& 3, Table 5 C161PI Registers, Ordered by Name (continued) Name Physical Address RTCH F0D6H E 6BH RTC High Register no RTCL F0D4H E 6AH RTC Low Register no S0BG FEB4H 5AH Serial Channel 0 Baud Rate Generator Reload Register 0000H S0CON b FFB0H D8H Serial Channel 0 Control Register 0000H S0EIC b FF70H B8H Serial Channel 0 Error Interrupt Control Register 0000H FEB2H 59H Serial Channel 0 Receive Buffer Reg.
& 3, Table 5 C161PI Registers, Ordered by Name (continued) Name Physical Address T14REL F0D0H E 68H T2 FE40H 20H GPT1 Timer 2 Register 0000H T2CON b FF40H A0H GPT1 Timer 2 Control Register 0000H T2IC b FF60H B0H GPT1 Timer 2 Interrupt Control Register 0000H FE42H 21H GPT1 Timer 3 Register 0000H T3CON b FF42H A1H GPT1 Timer 3 Control Register 0000H T3IC b FF62H B1H GPT1 Timer 3 Interrupt Control Register 0000H FE44H 22H GPT1 Timer 4 Register 0000H T4CON b FF44H A
& 3, Absolute Maximum Ratings Table 6 Absolute Maximum Rating Parameters Parameter Symbol Limit Values min. Unit Notes max. 7ST 9DD -65 150 °C -0.5 6.5 V 9IN -0.5 9DD+0.5 V Input current on any pin during overload condition -10 10 mA Absolute sum of all input currents during overload condition - |100| mA 1.
& 3, Operating Conditions The following operating conditions must not be exceeded in order to ensure correct operation of the C161PI. All parameters specified in the following sections refer to these operating conditions, unless otherwise noticed. Table 7 Operating Condition Parameters Parameter Symbol Limit Values min. Standard digital supply voltage Reduced digital supply voltage 9DD 9DD 9SS ,OV Overload current Absolute sum of overload Σ|,OV| Unit Notes max. 4.5 5.
& 3, Parameter Interpretation The parameters listed in the following partly represent the characteristics of the C161PI and partly its demands on the system. To aid in interpreting the parameters right, when evaluating them for a design, they are marked in column “Symbol”: CC (Controller Characteristics): The logic of the C161PI will provide signals with the respective timing characteristics.
& 3, DC Characteristics (Standard Supply Voltage Range) (continued) (Operating Conditions apply) Parameter Symbol Limit Values min. Unit Test Condition max. Output low voltage (all other outputs) 9OL1 CC – 0.45 V ,OL = 1.6 mA Output high voltage 1) (PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT, RSTOUT) 9OH CC 2.4 – V ,OH = -2.4 mA 0.9 9DD – V ,OH = -0.5 mA Output high voltage 1) (all other outputs) 9OH1 CC 2.4 – V 0.
& 3, DC Characteristics (Standard Supply Voltage Range) (continued) (Operating Conditions apply) Parameter Symbol Power-down mode supply current (5V) with RTC running ,PDR5 Power-down mode supply current (5V) with RTC disabled ,PDO5 Limit Values min. 8) – – Unit Test Condition max. 200 + µA 25*IOSC 9DD = 9DDmax IOSC in [MHz] 9) µA 9DD = 9DDmax 9) 50 1) This specification is not valid for outputs which are switched to open drain mode.
& 3, DC Characteristics (Reduced Supply Voltage Range) (Operating Conditions apply) Parameter Symbol Limit Values min. Unit Test Condition max. Input low voltage XTAL1, P3.0, P3.1, P6.5, P6.6, P6.7 9IL1 SR – 0.5 0.3 VDD V – Input low voltage (TTL) 9IL SR – 0.5 0.8 V – Input low voltage (Special Threshold) 9ILS SR – 0.5 1.3 V – Input high voltage RSTIN 9IH1 SR 0.6 9DD 9DD + V – V – V – V – 0.5 Input high voltage XTAL1, P3.0, P3.1, P6.5, P6.6, P6.7 9IH2 SR 0.
& 3, DC Characteristics (continued) (Reduced Supply Voltage Range) (Operating Conditions apply) Parameter Symbol Limit Values min. ,RSTL ,RWH 3) ,RWL 4) ,ALEL 3) ,ALEH 4) ,P6H 3) ,P6L 4) ,P0H 3) ,P0L 4) ,IL CC &IO CC Unit Test Condition max. 9IN = 9IL 9OUT = 2.4 V 9OUT = 9OLmax 9OUT = 9OLmax 9OUT = 2.4 V 9OUT = 2.
& 3, 7) The supply current is a function of the operating frequency. This dependency is illustrated in the figure below. These parameters are tested at 9DDmax and maximum CPU clock with all outputs disconnected and all inputs at 9IL or 9IH. The oscillator also contributes to the total supply current. The given values refer to the worst case, ie. IPDRmax. For lower oscillator frequencies the respective supply current can be reduced accordingly.
& 3, , [mA] IDD5max 50 IDD5typ 25 IDD3max IDD3typ IID5max IID5typ IID3max IID3typ 5 5 Figure 10 Data Sheet 10 15 20 25 ICPU [MHz] Supply/Idle Current as a Function of Operating Frequency 44 1999-07
& 3, AC Characteristics Definition of Internal Timing The internal operation of the C161PI is controlled by the internal CPU clock fCPU. Both edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles) operations. The specification of the external timing (AC Characteristics) therefore depends on the time between two consecutive edges of the CPU clock, called “TCL” (see figure below).
& 3, Table 8 P0.15-13 (P0H.7-5) 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 C161PI Clock Generation Modes CPU Frequency External Clock ICPU = IOSC * F Input Range 1) IOSC * 4 IOSC * 3 IOSC * 2 IOSC * 5 IOSC * 1 IOSC * 1.5 IOSC / 2 IOSC * 2.5 2.5 to 6.25 MHz Notes Default configuration 3.33 to 8.33 MHz 5 to 12.5 MHz 2 to 5 MHz 1 to 25 MHz Direct drive 2) 6.66 to 16.6 MHz 2 to 50 MHz CPU clock via prescaler 4 to 10 MHz 1) The external clock input range refers to a CPU clock range of 10...
& 3, The timings listed in the AC Characteristics that refer to TCLs therefore must be calculated using the minimum TCL that is possible under the respective circumstances. The actual minimum value for TCL depends on the jitter of the PLL. As the PLL is constantly adjusting its output frequency so it corresponds to the applied input frequency (crystal or oscillator) the relative deviation for periods of more than one TCL is lower than for one single TCL (see formula and figure below).
& 3, Direct Drive When pins P0.15-13 (P0H.7-5) equal 011B during reset the on-chip phase locked loop is disabled and the CPU clock is directly driven from the internal oscillator with the input clock signal. The frequency of ICPU directly follows the frequency of IOSC so the high and low time of ICPU (i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock IOSC.
& 3, AC Characteristics External Clock Drive XTAL1 (Standard Supply Voltage Range) (Operating Conditions apply) Parameter Symbol Direct Drive 1:1 min. Oscillator period WOSC SR High time 2) Low time 2) Rise time 2) Fall time 2) W1 W2 W3 W4 40 max. Prescaler 2:1 min. max. PLL 1:N min. Unit max.
& 3, Figure 13 External Clock Drive XTAL1 Note: The main oscillator is optimized for oscillation with a crystal within a frequency range of 4...16 MHz. When driven by an external clock signal it will accept the specified frequency range. Operation at lower input frequencies is possible but is guaranteed by design only (not 100% tested).
& 3, A/D Converter Characteristics (Operating Conditions apply) 4.0V (2.6V) ≤ 9AREF ≤ 9DD + 0.1V (Note the influence on TUE.) 9SS - 0.1V ≤ 9AGND ≤ 9SS + 0.2V Parameter Symbol Limit Values min. Analog input voltage range Basic clock frequency Conversion time Total unadjusted error Unit Test Condition max. 9AIN SR 9AGND IBC 0.5 WC CC – 9AREF V 1) 6.
& 3, Sample time and conversion time of the C161PI’s A/D Converter are programmable. The table below should be used to calculate the above timings. The limit values for IBC must not be exceeded when selecting ADCTC. Table 9 A/D Converter Computation Table ADCON.15|14 (ADCTC) A/D Converter Basic clock IBC ADCON.
& 3, Testing Waveforms 2.4 V 1.8 V 1.8 V Test Points 0.45 V 0.8 V 0.8 V AC inputs during testing are driven at 2.4 V for a logic ‘1’ and 0.45 V for a logic ‘0’. Timing measurements are made at 9IH min for a logic ’1’ and 9IL max for a logic ’0’. Figure 14 Input Output Waveforms For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs, but begins to float when a 100 mV change from the loaded 9OH/9OL level occurs (,OH/,OL = 20 mA).
& 3, AC Characteristics Multiplexed Bus (Standard Supply Voltage Range) (Operating Conditions apply) ALE cycle time = 6 TCL + 2WA + WC + WF (120 ns at 25 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 25 MHz 1 / 2TCL = 1 to 25 MHz min. max. min. max.
& 3, Multiplexed Bus (Standard Supply Voltage Range) (continued) (Operating Conditions apply) ALE cycle time = 6 TCL + 2WA + WC + WF (120 ns at 25 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 25 MHz 1 / 2TCL = 1 to 25 MHz min. max. min. max.
& 3, Multiplexed Bus (Standard Supply Voltage Range) (continued) (Operating Conditions apply) ALE cycle time = 6 TCL + 2WA + WC + WF (120 ns at 25 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 25 MHz 1 / 2TCL = 1 to 25 MHz min. max. min. max.
& 3, AC Characteristics Multiplexed Bus (Reduced Supply Voltage Range) (Operating Conditions apply) ALE cycle time = 6 TCL + 2WA + WC + WF (150 ns at 20 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 20 MHz 1 / 2TCL = 1 to 20 MHz min. max. min. max.
& 3, Multiplexed Bus (Reduced Supply Voltage Range) (continued) (Operating Conditions apply) ALE cycle time = 6 TCL + 2WA + WC + WF (150 ns at 20 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 20 MHz 1 / 2TCL = 1 to 20 MHz min. max. min. max.
& 3, Multiplexed Bus (Reduced Supply Voltage Range) (continued) (Operating Conditions apply) ALE cycle time = 6 TCL + 2WA + WC + WF (150 ns at 20 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 20 MHz 1 / 2TCL = 1 to 20 MHz min. max. min. max.
& 3, W5 W16 W25 ALE W38 W39 W40 CSxL W17 A22-A16 (A15-A8) BHE, CSxE W27 Address W6 W7 W54 W19 W18 5HDG &\FOH BUS Address W8 Data In W10 W14 RD W42 W44 W12 W51 W46 RdCSx W52 W48 :ULWH &\FOH BUS W23 Address W8 WR, WRL, WRH W42 Data Out W10 W22 W56 W12 W44 W50 WrCSx W48 Figure 16 Data Sheet External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Normal ALE 60 1999-07
& 3, W5 W16 W25 W39 W40 W17 W27 ALE W38 CSxL A22-A16 (A15-A8) BHE, CSxE Address W6 W7 W54 W19 W18 5HDG &\FOH BUS Address Data In W10 W8 W14 RD W44 W42 W12 W51 W46 RdCSx W52 W48 :ULWH &\FOH BUS W23 Address Data Out W10 W8 WR, WRL, WRH W44 W42 W22 W56 W12 W50 WrCSx W48 Figure 17 External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Extended ALE Data Sheet 61 1999-07
& 3, W5 W16 W25 ALE W38 W39 W40 CSxL W17 A22-A16 (A15-A8) BHE, CSxE W27 Address W6 W7 W54 W19 W18 5HDG &\FOH BUS Address W9 Data In W11 RD W43 W15 W13 W45 RdCSx W51 W47 W52 W49 :ULWH &\FOH BUS W23 Address W9 WR, WRL, WRH W43 Data Out W11 W22 W45 W13 W50 W56 WrCSx W49 Figure 18 Data Sheet External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Normal ALE 62 1999-07
& 3, W5 W16 W25 W39 W40 W17 W27 ALE W38 CSxL A22-A16 (A15-A8) BHE, CSxE Address W6 W7 W54 W19 W18 5HDG &\FOH BUS Address Data In W9 W11 RD W15 W13 W43 W45 RdCSx W51 W47 W52 W49 :ULWH &\FOH BUS W23 Address W9 WR, WRL, WRH Data Out W11 W22 W56 W13 W43 W45 W50 WrCSx W49 Figure 19 Data Sheet External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Extended ALE 63 1999-07
& 3, AC Characteristics Demultiplexed Bus (Standard Supply Voltage Range) (Operating Conditions apply) ALE cycle time = 4 TCL + 2WA + WC + WF (80 ns at 25 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 25 MHz 1 / 2TCL = 1 to 25 MHz min. max. min. max.
& 3, Demultiplexed Bus (Standard Supply Voltage Range) (continued) (Operating Conditions apply) ALE cycle time = 4 TCL + 2WA + WC + WF (80 ns at 25 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 25 MHz 1 / 2TCL = 1 to 25 MHz min. W24 CC 10 + WF Data hold after WR max. min. max.
& 3, Demultiplexed Bus (Standard Supply Voltage Range) (continued) (Operating Conditions apply) ALE cycle time = 4 TCL + 2WA + WC + WF (80 ns at 25 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 25 MHz 1 / 2TCL = 1 to 25 MHz min. max. min. max.
& 3, AC Characteristics Demultiplexed Bus (Reduced Supply Voltage Range) (Operating Conditions apply) ALE cycle time = 4 TCL + 2WA + WC + WF (100 ns at 20 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 20 MHz 1 / 2TCL = 1 to 20 MHz min. max. min. max.
& 3, Demultiplexed Bus (Reduced Supply Voltage Range) (continued) (Operating Conditions apply) ALE cycle time = 4 TCL + 2WA + WC + WF (100 ns at 20 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 20 MHz 1 / 2TCL = 1 to 20 MHz min. W24 CC 15 + WF Data hold after WR max. min. max.
& 3, Demultiplexed Bus (Reduced Supply Voltage Range) (continued) (Operating Conditions apply) ALE cycle time = 4 TCL + 2WA + WC + WF (100 ns at 20 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 20 MHz 1 / 2TCL = 1 to 20 MHz min. max. min. max.
& 3, W5 W16 W26 ALE W38 W39 W41 CSxL W17 A22-A16 A15-A0 BHE, CSxE W28 Address W6 W55 W20 W18 5HDG &\FOH BUS (D15-D8) D7-D0 Data In W8 W14 RD W12 W42 RdCSx W51 W46 W53 W48 :ULWH &\FOH BUS (D15-D8) D7-D0 WR, WRL, WRH W24 Data Out W8 W22 W57 W12 W42 W50 WrCSx W48 Figure 20 External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Normal ALE Data Sheet 70 1999-07
& 3, W5 W16 W26 ALE W38 W39 W41 CSxL A22-A16 A15-A0 BHE, CSxE W17 W28 Address W6 W55 W20 W18 5HDG &\FOH BUS (D15-D8) D7-D0 Data In W8 W14 RD W12 W42 W51 W46 RdCSx W53 W48 :ULWH &\FOH BUS (D15-D8) D7-D0 WR, WRL, WRH W24 Data Out W8 W22 W57 W12 W42 W50 WrCSx W48 Figure 21 Data Sheet External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Extended ALE 71 1999-07
& 3, W5 W16 W26 ALE W38 W39 W41 CSxL W17 A22-A16 A15-A0 BHE, CSxE W28 Address W6 5HDG &\FOH BUS (D15-D8) D7-D0 W55 W21 W18 Data In W9 W15 RD W43 W13 W51 W47 RdCSx W68 W49 :ULWH &\FOH BUS (D15-D8) D7-D0 W24 Data Out W9 W22 WR, WRL,WRH W57 W13 W50 W43 WrCSx W49 Figure 22 External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Normal ALE Data Sheet 72 1999-07
& 3, W5 W16 W26 ALE W38 W39 W41 CSxL W17 A22-A16 A15-A0 BHE,CSxE W28 Address W6 W55 W21 W18 5HDG &\FOH BUS (D15-D8) D7-D0 Data In W9 W15 RD W13 W43 W51 W47 RdCSx W68 W49 :ULWH &\FOH BUS (D15-D8) D7-D0 W24 Data Out W9 W22 WR, WRL, WRH W57 W13 W43 W50 WrCSx W49 Figure 23 External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Extended ALE Data Sheet 73 1999-07
& 3, AC Characteristics CLKOUT and READY (Standard Supply Voltage Range) (Operating Conditions apply) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 25 MHz 1 / 2TCL = 1 to 25 MHz min. CLKOUT cycle time CLKOUT high time CLKOUT low time CLKOUT rise time CLKOUT fall time CLKOUT rising edge to ALE falling edge W29 W30 W31 W32 W33 W34 max. min. max.
& 3, AC Characteristics CLKOUT and READY (Reduced Supply Voltage Range) (Operating Conditions apply) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 20 MHz 1 / 2TCL = 1 to 20 MHz min. CLKOUT cycle time CLKOUT high time CLKOUT low time CLKOUT rise time CLKOUT fall time CLKOUT rising edge to ALE falling edge W29 W30 W31 W32 W33 W34 max. min. max.
& 3, READY waitstate Running cycle 1) CLKOUT W32 MUX/Tristate 6) W33 W30 W29 W31 W34 ALE 7) Command RD, WR 2) W35 Sync READY W59 W36 3) W58 W59 3) W60 4) 3) 5) Figure 24 W35 3) W58 Async READY W36 W37 see 6) CLKOUT and READY Notes 1) Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS). 2) The leading edge of the respective command depends on RW-delay.
& 3, Package Outlines Plastic Package, P-MQFP-100-2 (SMD) (Plastic Metric Quad Flat Package) Figure 25 Data Sheet 77 1999-07
C161PI Package Outlines (continued) Plastic Package, P-TQFP-100-1 (SMD) (Plastic Thin Metric Quad Flat Package) Figure 26 Sorts of Packing Package outlines for tubes, trays, etc.
& 3, Data Sheet 79 1999-07
& 3, Published by Infineon Technologies AG Data Sheet 80 1999-07
