Datasheet

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Data Sheet 16 1999-07
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Central Processing Unit (CPU)
The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic
and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a
separate multiply and divide unit, a bit-mask generator and a barrel shifter.
Based on these hardware provisions, most of the C161PI’s instructions can be executed
in just one machine cycle which requires 2 CPU clocks (4 TCL). For example, shift and
rotate instructions are always processed during one machine cycle independent of the
number of bits to be shifted. All multiple-cycle instructions have been optimized so that
they can be executed very fast as well: branches in 2 cycles, a 16 × 16 bit multiplication
in 5 cycles and a 32-/16 bit division in 10 cycles. Another pipeline optimization, the so-
called ‘Jump Cache’, reduces the execution time of repeatedly performed jumps in a loop
from 2 cycles to 1 cycle.
Figure 5 CPU Block Diagram