Datasheet
&3,
Data Sheet 45 1999-07
AC Characteristics
Definition of Internal Timing
The internal operation of the C161PI is controlled by the internal CPU clock f
CPU
. Both
edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles)
operations.
The specification of the external timing (AC Characteristics) therefore depends on the
time between two consecutive edges of the CPU clock, called “TCL” (see figure below).
Figure 11 Generation Mechanisms for the CPU Clock
The CPU clock signal
I
CPU
can be generated from the oscillator clock signal I
OSC
via
different mechanisms. The duration of TCLs and their variation (and also the derived
external timing) depends on the used mechanism to generate
I
CPU
. This influence must
be regarded when calculating the timings for the C161PI.
Note: The example for PLL operation shown in the fig. above refers to a PLL factor of 4.
The used mechanism to generate the CPU clock is selected during reset via the logic
levels on pins P0.15-13 (P0H.7-5).
The table below associates the combinations of these three bits with the respective clock
generation mode.
TCLTCL
TCLTCL
I
I
I
I
3KDVH/RFNHG/RRS2SHUDWLRQ
'LUHFW&ORFN'ULYH
TCL TCL
I
I
3UHVFDOHU2SHUDWLRQ