Datasheet

&3,
Data Sheet 54 1999-07

AC Characteristics
Multiplexed Bus (Standard Supply Voltage Range)
(Operating Conditions apply)
ALE cycle time = 6 TCL + 2
W
A
+ W
C
+ W
F
(120 ns at 25 MHz CPU clock without waitstates)
Parameter Symbol Max. CPU Clock
= 25 MHz
Variable CPU Clock
1 / 2TCL = 1 to 25 MHz
Unit
min. max. min. max.
ALE high time
W
5
CC 10 + W
A
– TCL - 10
+

W
A
–ns
Address setup to ALE
W
6
CC 4 +

W
A
– TCL - 16
+

W
A
–ns
Address hold after ALE
W
7
CC 10 +

W
A
– TCL - 10
+

W
A
–ns
ALE falling edge to RD
,
WR
(with RW-delay)
W
8
CC 10 +

W
A
– TCL - 10
+

W
A
–ns
ALE falling edge to RD
,
WR
(no RW-delay)
W
9
CC -10 +

W
A
–-10 +

W
A
–ns
Address float after RD
,
WR
(with RW-delay)
W
10
CC–6–6ns
Address float after RD
,
WR
(no RW-delay)
W
11
CC – 26 – TCL + 6 ns
RD
, WR low time
(with RW-delay)
W
12
CC 30 +

W
C
– 2TCL - 10
+

W
C
–ns
RD
, WR low time
(no RW-delay)
W
13
CC 50 +

W
C
–3TCL-
10+
W
C
–ns
RD
to valid data in
(with RW-delay)
W
14
SR – 20 +W
C
– 2TCL - 20
+
W
C
ns
RD
to valid data in
(no RW-delay)
W
15
SR – 40 +W
C
– 3TCL - 20
+
W
C
ns
ALE low to valid data in
W
16
SR – 40 + W
A
+ W
C
– 3TCL - 20
+
W
A
+W
C
ns
Address to valid data in
W
17
SR – 50 + 2W
A
+ W
C
– 4TCL - 30
+2
W
A
+W
C
ns
Data hold after RD
rising edge
W
18
SR0–0–ns
Data float after RD
W
19
SR – 26 +W
F
– 2TCL - 14
+
W
F
ns