Datasheet

&3,
Data Sheet 56 1999-07

Data valid to WrCS W
50
CC 26 +

W
C
– 2TCL - 14
+

W
C
–ns
Data hold after RdCS
W
51
SR0–0–ns
Data float after RdCS
W
52
SR – 20 +

W
F
– 2TCL - 20
+

W
F
ns
Address hold after
RdCS
, WrCS
W
54
CC 20 +

W
F
– 2TCL - 20
+

W
F
–ns
Data hold after WrCS
W
56
CC 20 +

W
F
– 2TCL - 20
+

W
F
–ns
1) These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are
specified together with the address and signal BHE
(see figures below).
Multiplexed Bus (Standard Supply Voltage Range) (continued)
(Operating Conditions apply)
ALE cycle time = 6 TCL + 2
W
A
+ W
C
+ W
F
(120 ns at 25 MHz CPU clock without waitstates)
Parameter Symbol Max. CPU Clock
= 25 MHz
Variable CPU Clock
1 / 2TCL = 1 to 25 MHz
Unit
min. max. min. max.