Datasheet

&3,
Data Sheet 58 1999-07

Data valid to WR W
22
CC 24 +

W
C
– 2TCL - 26
+

W
C
–ns
Data hold after WR
W
23
CC 36 +

W
F
– 2TCL - 14
+

W
F
–ns
ALE rising edge after RD
,
WR
W
25
CC 36 +

W
F
– 2TCL - 14
+

W
F
–ns
Address hold after RD
,
WR
W
27
CC 36 +

W
F
– 2TCL - 14
+

W
F
–ns
ALE falling edge to CS
1)
W
38
CC -8 -

W
A
10 - W
A
-8 -

W
A
10 -

W
A
ns
CS
low to Valid Data In
1)
W
39
SR – 47
+

W
C
+

2W
A
– 3TCL - 28
+

W
C
+ 2W
A
ns
CS
hold after RD, WR
1)
W
40
CC 57 +

W
F
– 3TCL - 18
+
W
F
–ns
ALE fall. edge to RdCS
,
WrCS
(with RW delay)
W
42
CC 19 +

W
A
– TCL - 6
+

W
A
–ns
ALE fall. edge to RdCS
,
WrCS
(no RW delay)
W
43
CC -6 +

W
A
–-6
+

W
A
–ns
Address float after RdCS
,
WrCS
(with RW delay)
W
44
CC–0–0ns
Address float after RdCS
,
WrCS
(no RW delay)
W
45
CC – 25 – TCL ns
RdCS
to Valid Data In
(with RW delay)
W
46
SR – 20 +W
C
– 2TCL - 30
+
W
C
ns
RdCS
to Valid Data In
(no RW delay)
W
47
SR – 45 +W
C
– 3TCL - 30
+
W
C
ns
RdCS
, WrCS Low Time
(with RW delay)
W
48
CC 38 +W
C
– 2TCL - 12
+
W
C
–ns
RdCS
, WrCS Low Time
(no RW delay)
W
49
CC 63 +W
C
– 3TCL - 12
+
W
C
–ns
Data valid to WrCS
W
50
CC 28 +W
C
– 2TCL - 22
+
W
C
–ns
Multiplexed Bus (Reduced Supply Voltage Range) (continued)
(Operating Conditions apply)
ALE cycle time = 6 TCL + 2
W
A
+ W
C
+ W
F
(150 ns at 20 MHz CPU clock without waitstates)
Parameter Symbol Max. CPU Clock
= 20 MHz
Variable CPU Clock
1 / 2TCL = 1 to 20 MHz
Unit
min. max. min. max.