Datasheet

&3,
Data Sheet 61 1999-07

Figure 17 External Memory Cycle:
Multiplexed Bus, With Read/Write Delay, Extended ALE
Data OutAddress
Data InAddress
W
38
W
44
W
10
Address
ALE
CSxL
A22-A16
(A15-A8)
BHE
, CSxE
BUS
5HDG &\FOH
RD
RdCSx
BUS
:ULWH &\FOH
WR,
WRL
,
WRH
WrCSx
W
5
W
16
W
17
W
6
W
7
W
39
W
40
W
25
W
27
W
18
W
19
W
14
W
46
W
12
W
48
W
10
W
22
W
23
W
44
W
12
W
48
W
8
W
42
W
42
W
8
W
50
W
51
W
54
W
52
W
56