Datasheet

&3,
Data Sheet 62 1999-07

Figure 18 External Memory Cycle:
Multiplexed Bus, No Read/Write Delay, Normal ALE
Data OutAddress
Address Data In
W
38
Address
ALE
CSxL
A22-A16
(A15-A8)
BHE
, CSxE
BUS
5HDG&\FOH
RD
RdCSx
BUS
:ULWH&\FOH
WR,
WRL
,
WRH
WrCSx
W
5
W
16
W
17
W
6
W
7
W
39
W
40
W
25
W
27
W
18
W
19
W
15
W
47
W
13
W
49
W
22
W
23
W
13
W
49
W
9
W
43
W
43
W
9
W
11
W
45
W
11
W
45
W
50
W
51
W
54
W
52
W
56