Datasheet

&3,
Data Sheet 67 1999-07

AC Characteristics
Demultiplexed Bus (Reduced Supply Voltage Range)
(Operating Conditions apply)
ALE cycle time = 4 TCL + 2
W
A
+ W
C
+ W
F
(100 ns at 20 MHz CPU clock without waitstates)
Parameter Symbol Max. CPU Clock
= 20 MHz
Variable CPU Clock
1 / 2TCL = 1 to 20 MHz
Unit
min. max. min. max.
ALE high time
W
5
CC 11 +

W
A
– TCL - 14
+

W
A
–ns
Address setup to ALE
W
6
CC 5 +

W
A
– TCL - 20
+

W
A
–ns
ALE falling edge to RD
,
WR
(with RW-delay)
W
8
CC 15 +

W
A
– TCL - 10
+

W
A
–ns
ALE falling edge to RD
,
WR
(no RW-delay)
W
9
CC -10 +

W
A
– -10
+

W
A
–ns
RD
, WR low time
(with RW-delay)
W
12
CC 34 +

W
C
– 2TCL - 16
+

W
C
–ns
RD
, WR low time
(no RW-delay)
W
13
CC 59 +

W
C
– 3TCL - 16
+

W
C
–ns
RD
to valid data in
(with RW-delay)
W
14
SR – 22 +

W
C
– 2TCL - 28
+

W
C
ns
RD
to valid data in
(no RW-delay)
W
15
SR – 47 +

W
C
– 3TCL - 28
+

W
C
ns
ALE low to valid data in
W
16
SR – 49 +
W
A
+

W
C
– 3TCL - 30
+

W
A
+

W
C
ns
Address to valid data in
W
17
SR – 57 +
2
W
A
+W
C
– 4TCL - 43
+2
W
A
+W
C
ns
Data hold after RD
rising edge
W
18
SR0–0–ns
Data float after RD
rising
edge (with RW-delay
1)
)
W
20
SR – 36 +
2
W
A
+W
F
1)
– 2TCL - 14
+2
W
A
+W
F
1)
ns
Data float after RD
rising
edge (no RW-delay
1)
)
W
21
SR – 15 +
2
W
A
+W
F
1)
– TCL - 10
+2
W
A
+
W
F
1)
ns
Data valid to WR
W
22
CC 24 +W
C
– 2TCL - 26
+
W
C
–ns