Datasheet

&3,
Data Sheet 70 1999-07

Figure 20 External Memory Cycle:
Demultiplexed Bus, With Read/Write Delay, Normal ALE
Data Out
Data In
W
38
Address
ALE
CSxL
A22-A16
A15-A0
BHE
, CSxE
BUS
(D15-D8)
D7-D0
5HDG &\FOH
RD
RdCSx
:ULWH &\FOH
WrCSx
W
5
W
16
W
17
W
6
W
39
W
41
W
26
W
28
W
18
W
20
W
14
W
46
W
12
W
48
W
22
W
24
W
12
W
48
W
8
W
42
W
42
W
8
W
50
W
51
W
55
W
53
W
57
BUS
(D15-D8)
D7-D0
WR,
WRL
,
WRH