Datasheet

&3,
Data Sheet 73 1999-07

Figure 23 External Memory Cycle:
Demultiplexed Bus, No Read/Write Delay, Extended ALE
Data Out
Data In
W
38
Address
ALE
CSxL
A22-A16
A15-A0
BHE
,CSxE
5HDG&\F OH
RD
RdCSx
:ULWH&\FOH
WR,
WRL
, WRH
WrCSx
W
5
W
16
W
17
W
6
W
39
W
41
W
26
W
28
W
18
W
21
W
15
W
47
W
13
W
49
W
22
W
24
W
13
W
49
W
9
W
43
W
43
W
9
W
50
W
51
W
55
W
68
W
57
BUS
(D15-D8)
D7-D0
BUS
(D15-D8)
D7-D0