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Microcontrollers

Data Sheet, Dec. 2000

C505

C505C

C505A

C505CA

8-Bit Single-Chip Microcontroller

Summary of content (88 pages)

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D at a S hee t, De c. 2 00 0 C505 C505C C505A C505CA 8-Bit Single-Chip Microcontroller Microcontrollers N e v e r s t o p t h i n k i n g .
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Edition 2000-12 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München, Germany © Infineon Technologies AG 2000. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved.
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Da ta She et, De c. 2 00 0 C505 C505C C505A C505CA 8-Bit Single-Chip Microcontroller Microcontrollers N e v e r s t o p t h i n k i n g .
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C505/C505C/C505A/C505CA Data Sheet Revision History : Current Version : 2000-12 Previous Releases : 08.00, 06.00, 07.99, 12.97 Page Page (in previous (in current version version) Subjects (major changes since last revision) 24 Version register VR2 for C505A-4R/C505CA-4R BB step is updated.
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8-Bit Single-Chip Microcontroller C500 Family C505/C505C/C505A/ C505CA Advance Information • Fully compatible to standard 8051 microcontroller • Superset of the 8051 architecture with 8 datapointers • Up to 20 MHz operating frequency • • • – 375 ns instruction cycle time @16 MHz – 300 ns instruction cycle time @20 MHz (50 % duty cycle) On-chip program memory (with optional memory protection) – C505(C)(A)-2R : 16K byte on-chip ROM – C505A-4R/C505CA-4R: 32K byte on-chip ROM – C505A-4E/C505CA-4E: 32K byte
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C505/C505C/C505A/C505CA Features (continued) : • 32 + 2 digital I/O lines • • • • • • • • • • • • • – Four 8-bit digital I/O ports – One 2-bit digital I/O port (port 4) – Port 1 with mixed analog/digital I/O capability Three 16-bit timers/counters – Timer 0 / 1 (C501 compatible) – Timer 2 with 4 channels for 16-bit capture/compare operation Full duplex serial interface with programmable baudrate generator (USART) Full CAN Module, version 2.
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C505/C505C/C505A/C505CA Table 1 Differences in Functionality of the C505 MCUs Device Internal Program Memory XRAM Size A/D Converter Resolution CAN Controller ROM OTP C505-2R 16K byte – 256 byte 8 Bit – C505-L – – 256 byte 8 Bit – C505C-2R 16K byte – 256 byte 8 Bit √ C505C-L – – 256 byte 8 Bit √ C505A-4R 32K byte – 1K byte 10 Bit – C505A-2R 16K byte – 1K byte 10 Bit – C505A-L – – 1K byte 10 Bit – C505CA-4R 32K byte – 1K byte 10 Bit √ C505CA-2R 16K byte
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C505/C505C/C505A/C505CA VDD VSS Port 0 8-bit Digital I/O VAREF VAGND XTAL1 XTAL2 RESET C505 C505C C505A C505CA Port 1 8-bit Digital I/O / 8-bit Analog Inputs Port 2 8-bit Digital I/O Port 3 8-bit Digital I/O EA ALE PSEN Port 4 2-bit Digital I/O Figure 2 Logic Symbol Note: The ordering codes for the Mask-ROM versions are defined for each product after verification of the respective ROM code. Data Sheet 4 12.
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P0.4 / AD4 P0.5 / AD5 P0.6 / AD6 P0.7 / AD7 EA P4.1 / RXDC ALE PSEN P2.7 / A15 P2.6 / A14 P2.5 / A13 C505/C505C/C505A/C505CA P0.3 / AD3 P0.2 / AD2 P0.1 / AD1 P0.0 / AD0 V AREF V AGND P1.0 / AN0 / INT3 / CC0 P1.1 / AN1 / INT4 / CC1 P1.2 / AN2 / INT5 / CC2 P1.3 / AN3 / INT6 / CC3 P1.4 / AN4 33 32 31 30 29 28 27 26 25 24 23 22 34 35 21 36 20 37 19 C505 C505C C505A C505CA 38 39 40 41 18 17 16 15 42 14 43 13 44 2 3 4 5 6 7 8 12 9 10 11 P1.5 / AN5 / T2EX P1.6 / AN6 / CLKOUT P1.
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C505/C505C/C505A/C505CA Table 2 Pin Definitions and Functions Symbol P1.0-P1.7 Pin Number 40-44,1-3 40 41 42 43 44 1 2 3 I/O *) Function I/O Port 1 is an 8-bit quasi-bidirectional port with internal pull-up arrangement. Port 1 pins can be used for digital input/output or as analog inputs of the A/D converter. Port 1 pins that have 1’s written to them are pulled high by internal pull-up transistors and in that state can be used as inputs.
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C505/C505C/C505A/C505CA Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Number I/O *) Function RESET 4 I RESET A high level on this pin for two machine cycle while the oscillator is running resets the device. An internal diffused resistor to V SS permits power-on reset using only an external capacitor to VDD. P3.0-P3.7 5, 7-13 I/O Port 3 is an 8-bit quasi-bidirectional port with internal pull-up arrangement.
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C505/C505C/C505A/C505CA Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Number I/O *) Function P4.0 P4.1 6 28 I/O I/O Port 4 is a 2-bit quasi-bidirectional port with internal pull-up arrangement. Port 4 pins that have 1’s written to them are pulled high by the internal pull-up transistors and in that state can be used as inputs. As inputs, port 4 pins being externally pulled low will source current (I IL , in the DC characteristics) because of the internal pullup transistors.
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C505/C505C/C505A/C505CA Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Number I/O *) Function P2.0-P2.7 18-25 I/O Port 2 is a an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 2 pins that have 1’s written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 2 pins being externally pulled low will source current (I IL , in the DC characteristics) because of the internal pullup resistors.
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C505/C505C/C505A/C505CA Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Number I/O *) Function EA 29 I External Access Enable When held at high level, instructions are fetched from the internal program memory when the PC is less than 4000H (C505(C)(A)-2R) or 8000H (C505A-4R/C505CA-4R/C505A4E/C505CA-4E). When held at low level, the C505 fetches all instructions from external program memory. For the C505 romless versions (i.e. C505-L, C505C-L, C505A-L and C505CA-L) this pin must be tied low.
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C505/C505C/C505A/C505CA VDD Vss Oscillator Watchdog XRAM 1) XTAL1 XTAL2 RESET OSC & Timing 256 Byte or 1K Byte RAM 256 Byte ROM/ OTP 1) 16K or 32K Byte CPU 8 datapointers ALE PSEN Programmable Watchdog Timer Port 0 Port 0 8-bit digit. I/O Port 1 Port 1 8-bit digit. I/O / 8-bit analog In Port 2 Port 2 8-bit digit. I/O Baudrate generator Port 3 Port 3 8-bit digit. I/O 256 Byte Reg./Data EA Port 4 Port 4 2-bit digit.
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C505/C505C/C505A/C505CA CPU The C505 is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44 % one-byte, 41 % two-byte, and 15% threebyte instructions. With a 16 MHz crystal, 58% of the instructions are executed in 375 ns (20MHz: 300 ns). Special Function Register PSW (Address D0H) Reset Value : 00H Bit No.
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C505/C505C/C505A/C505CA Memory Organization The C505 CPU manipulates operands in the following four address spaces: – On-chip program memory :16K byte ROM (C505(C)(A)-2R) or 32K byte ROM (C505A-4R/C505CA-4R) or 32K byte OTP (C505A-4E/C505CA-4E) – Totally up to 64K byte internal/external program memory – up to 64 Kbyte of external data memory – 256 bytes of internal data memory – Internal XRAM data memory :256 byte (C505/C505C) 1K byte (C505A/C505CA) – a 128 byte special function register area Figure 5 illu
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C505/C505C/C505A/C505CA Reset and System Clock The reset input is an active high input at pin RESET. Since the reset is synchronized internally, the RESET pin must be held high for at least two machine cycles (12 oscillator periods) while the oscillator is running. A pulldown resistor is internally connected to VSS to allow a power-up reset with an external capacitor only. An automatic reset can be obtained when VDD is applied by connecting the RESET pin to VDD via a capacitor.
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C505/C505C/C505A/C505CA Figure 7 shows the recommended oscillator circuits for crystal and external clock operation. C XTAL2 C505 C505C C505A C505CA 2-20 MHz C XTAL1 C = 20pF ± 10pF for crystal operation C = 20 pF ± 10pF for crystal operation N.C. VDD XTAL2 C505 C505C C505A C505CA External Clock Signal XTAL1 Figure 7 Recommended Oscillator Circuitries Data Sheet 15 12.
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C505/C505C/C505A/C505CA Multiple Datapointers As a functional enhancement to the standard 8051 architecture, the C505 contains eight 16-bit datapointers instead of only one datapointer. The instruction set uses just one of these datapointers at a time. The selection of the actual datapointer is done in the special function regsiter DPSEL. Figure 8 illustrates the datapointer addressing mechanism. - - - - - .2 .1 .0 DPSEL(92 H) DPSEL DPTR7 Selected Data- .2 .1 .
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C505/C505C/C505A/C505CA Enhanced Hooks Emulation Concept The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative way to control the execution of C500 MCUs and to gain extensive information on the internal operation of the controllers. Emulation of on-chip ROM based programs is possible, too. Each production chip has built-in logic for the supprt of the Enhanced Hooks Emulation Concept. Therefore, no costly bond-out chips are necessary for emulation.
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C505/C505C/C505A/C505CA Special Function Registers The registers, except the program counter and the four general purpose register banks, reside in the special function register area. The special function register area consists of two portions : the standard special function register area and the mapped special function register area. Five special function register of the C505 (PCON1,P1ANA, VR0, VR1, VR2) are located in the mapped special function register area.
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C505/C505C/C505A/C505CA Table 3 Special Function Registers - Functional Blocks Block Symbol Name Address Contents after Reset CPU ACC B DPH DPL DPSEL PSW SP SYSCON2) Accumulator B-Register Data Pointer, High Byte Data Pointer, Low Byte Data Pointer Select Register Program Status Word Register Stack Pointer System Control Register E0H 1) F0H 1) 83H 82H 92H D0H 1) 81H B1H VR0 4) VR1 4) VR2 4) Version Register 0 Version Register 1 Version Register 2 FCH FDH FEH 00H 00H 00H 00H XXXXX000B 3) 00H 07H
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C505/C505C/C505A/C505CA Table 3 Special Function Registers - Functional Blocks (cont’d) Block Symbol Name Address Contents after Reset Ports P0 P1 P1ANA 2) 4) P2 P3 P4 Port 0 Port 1 Port 1 Analog Input Selection Register Port 2 Port 3 Port 4 80H 1) 90H 1) 90H 1) A0H 1) B0H 1) E8H 1) FFH FFH FFH FFH FFH XXXXXX11B Serial Channel ADCON0 2) PCON 2) SBUF SCON SRELL SRELH A/D Converter Control Register 0 Power Control Register Serial Channel Buffer Register Serial Channel Control Register Serial Chan
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C505/C505C/C505A/C505CA Table 3 Special Function Registers - Functional Blocks (cont’d) Block Symbol CAN CR Controller SR IR (C505C/ BTR0 C505CA BTR1 only) GMS0 GMS1 UGML0 UGML1 LGML0 LGML1 UMLM0 UMLM1 LMLM0 LMLM1 MCR0 MCR1 UAR0 UAR1 LAR0 LAR1 MCFG DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 Name Address Contents after Reset Control Register Status Register Interrupt Register Bit Timing Register Low Bit Timing Register High Global Mask Short Register Low Global Mask Short Register High Upper Global Mask Long Reg
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C505/C505C/C505A/C505CA Table 4 Contents of the SFRs, SFRs in numeric order of their addresses Addr Register Content Bit 7 after Reset1) 80H 2) P0 81H SP Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FFH .7 .6 .5 .4 .3 .2 .1 .0 07H .7 .6 .5 .4 .3 .2 .1 .0 82H 83H DPL 00H .7 .6 .5 .4 .3 .2 .1 .0 DPH 00H .7 .6 .5 .4 .3 .2 .1 .0 86H WDTREL 00H WDT PSEL .6 .5 .4 .3 .2 .1 .
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C505/C505C/C505A/C505CA Table 4 Contents of the SFRs, SFRs in numeric order of their addresses (cont’d) Addr Register Content Bit 7 after Reset1) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 B0H2) P3 RD WR T1 T0 INT1 INT0 TxD RxD SYSCON XX100X01B – – EALE RMAP CMOD – SYSCON XX104) 0001B – – EALE RMAP CMOD CSWO XMAP1 XMAP0 B1H FFH XMAP1 XMAP0 3) B1H B8H 2) IEN1 00H EXEN2 SWDT EX6 EX5 EX4 EX3 ECAN EADC B9H IP1 – – .5 .4 .3 .2 .1 .
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C505/C505C/C505A/C505CA Table 4 Contents of the SFRs, SFRs in numeric order of their addresses (cont’d) Addr Register Content Bit 7 after Reset1) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 D9H ADDAT 6) 00H ADDATH 00H .7 .6 .5 .4 .3 .2 .1 .0 .9 .8 .7 .6 .5 .4 .3 .2 XXXXXXXXB – – – – – – – – 00XXXXXXB .1 .0 – – – – – – D9H 7) 6) DAH ADST DAH ADDATL 7) DCH ADCON1 01XXX000B ADCL1 ADCL0 – – – MX2 MX1 MX0 E0H2) ACC 00H .7 .6 .5 .4 .3 .2 .1 .
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C505/C505C/C505A/C505CA Table 5 Contents of the CAN Registers in numeric order of their addresses (C505C/C505CA only) Register Content Bit 7 Addr. after n=1-FH 1) Reset 2) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 F700H CR 01H TEST CCE 0 0 EIE SIE IE INIT F701H SR BOFF EWRN – LEC2 LEC1 LEC0 F702H IR XXH XXH F704H BTR0 UUH F705H BTR1 0UUU. 0 UUUUB F706H GMS0 UUH F707H GMS1 UUU1.
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C505/C505C/C505A/C505CA Table 5 Contents of the CAN Registers in numeric order of their addresses (cont’d) (C505C/C505CA only) Register Content Bit 7 Addr. after n=1-FH 1) Reset 2) Bit 6 Bit 5 Bit 4 Bit 2 Bit 1 Bit 0 DIR XTD 0 0 F7n6H MCFG UUUU. UU00B F7n7H DB0 .7 .6 .5 .4 .3 .2 .1 .0 F7n8H DB1 XXH XXH .7 .6 .5 .4 .3 .2 .1 .0 F7n9H DB2 .7 .6 .5 .4 .3 .2 .1 .0 F7nAH DB3 XXH XXH .7 .6 .5 .4 .3 .2 .1 .0 F7nBH DB4 XXH XXH .7 .6 .5 .4 .3 .2 .1 .
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C505/C505C/C505A/C505CA I/O Ports The C505 has four 8-bit I/O ports and one 2-bit I/O port. Port 0 is an open-drain bidirectional I/O port, while ports 1 to 4 are quasi-bidirectional I/O ports with internal pullup resistors. That means, when configured as inputs, ports 1 to 4 will be pulled high and will source current when externally pulled low. Port 0 will float when configured as input. The output drivers of port 0 and 2 and the input buffers of port 0 are also used for accessing external memory.
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C505/C505C/C505A/C505CA Timer / Counter 0 and 1 Timer/Counter 0 and 1 can be used in four operating modes as listed in Table 6 : Table 6 Timer/Counter 0 and 1 Operating Modes Mode Description TMOD Input Clock M1 M0 internal external (max) fOSC/6x32 fOSC/12x32 fOSC/6 fOSC/12 0 8-bit timer/counter with a divide-by-32 prescaler 0 0 1 16-bit timer/counter 0 1 2 8-bit timer/counter with 8-bit autoreload 1 0 3 Timer/counter 0 used as one 8-bit timer/counter and one 8-bit timer Timer 1 st
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C505/C505C/C505A/C505CA Timer/Counter 2 with Compare/Capture/Reload The timer 2 of the C505 provides additional compare/capture/reload features.
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C505/C505C/C505A/C505CA Timer 2 Operating Modes The timer 2, which is a 16-bit-wide register, can operate as timer, event counter, or gated timer. A roll-over of the count value in TL2/TH2 from all 1’s to all 0’s sets the timer overflow flag TF2 in SFR IRCON, which can generate an interrupt. The bits in register T2CON are used to control the timer 2 operation. Timer Mode : In timer function, the count rate is derived from the oscillator frequency.
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C505/C505C/C505A/C505CA Timer 2 Compare Modes The compare function of a timer/register combination operates as follows : the 16-bit value stored in a compare or compare/capture register is compared with the contents of the timer register; if the count value in the timer register matches the stored value, an appropriate output signal is generated at a corresponding port pin and an interrupt can be generated.
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C505/C505C/C505A/C505CA Compare Mode 1 If compare mode 1 is enabled and the software writes to the appropriate output latch at the port, the new value will not appear at the output pin until the next compare match occurs. Thus, it can be choosen whether the output signal has to make a new transition (1-to-0 or 0-to-1, depending on the actual pin-level) or should keep its old value at the time when the timer value matches the stored compare value.
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C505/C505C/C505A/C505CA Serial Interface (USART) The serial port is full duplex and can operate in four modes (one synchronous mode, three asynchronous modes) as illustrated in Table 7.
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C505/C505C/C505A/C505CA Timer 1 Overflow f OSC ADCON0.7 (BD) Baud Rate Generator Mode 1 Mode 3 0 1 SCON.7 SCON.6 (SM0/ SM1) ÷2 PCON.7 (SMOD) 0 1 (SRELH SRELL) Baud Rate Clock Mode 2 Only one mode can be selected Mode 0 ÷6 Note: The switch configuration shows the reset state.
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C505/C505C/C505A/C505CA CAN Controller (C505C and C505CA only) The on-chip CAN controller, compliant to version 2.0B, is the functional heart which provides all resources that are required to run the standard CAN protocol (11-bit identifiers) as well as the extended CAN protocol (29-bit identifiers). It provides a sophisticated object layer to relieve the CPU of as much overhead as possible when controlling many different message objects (up to 15).
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C505/C505C/C505A/C505CA TXDC RXDC BTL-Configuration CRC Gen./Check Bit Timing Logic Timing Generator TX/RX Shift Register Messages Messages Handlers Clocks (to all) Control Intelligent Memory Interrupt Register Status + Control Bit Stream Processor Error Management Logic Status Register to internal Bus MCB02736 Figure 15 CAN Controller Block Diagram Data Sheet 36 12.
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C505/C505C/C505A/C505CA CAN Controller Software Initialization The very first step of the initialization is the CAN controller input clock selection. A divide-by-2 prescaler is enabled by default after reset (Figure 16). Setting bit CMOD (SYSCON.3) disables the prescaler. The purpose of the prescaler selection is: – to ensure that the CAN controller is operable when fosc is over 10 MHz (bit CMOD =0) – to achieve the maximum CAN baudrate of 1 Mbaud when fosc is 8 MHz (bit CMOD=1) SYSCON.
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C505/C505C/C505A/C505CA 8-Bit A/D Converter (C505 and C505C only) The C505/C505C includes a high performance / high speed 8-bit A/D converter (ADC) with 8 analog input channels.
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C505/C505C/C505A/C505CA Internal Bus IEN1 (B8 H ) EXEN2 EX6 EX5 EX4 EX3 ECAN EADC TF2 IEX6 IEX5 IEX4 IEX3 SWI IADC EAN6 EAN5 EAN4 EAN3 EAN2 EAN1 EAN0 MX2 MX1 MX0 MX2 MX1 MX0 SWDT IRCON (C0 H ) EXF2 P1ANA (90 H ) EAN7 ADCON1 (DC H ) ADCL1 ADCL0 ADCON0 (D8 H ) BD CLK BSY ADM Single / Continuous Mode Port 1 ADDAT ADST (D9 H ) (DA H ) LSB MUX .1 S&H .2 .3 Conversion Clock Prescaler f OSC Conversion Clock f ADC A/D Converter Input Clock f IN .4 .5 .
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C505/C505C/C505A/C505CA 10-Bit A/D Converter (C505A and C505CA only) The C505A/C505CA includes a high performance / high speed 10-bit A/D-Converter (ADC) with 8 analog input channels. It operates with a successive approximation technique and uses self calibration mechanisms for reduction and compensation of offset and linearity errors.
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C505/C505C/C505A/C505CA Internal Bus IEN1 (B8 H ) EXEN2 EX6 EX5 EX4 EX3 ECAN EADC TF2 IEX6 IEX5 IEX4 IEX3 SWI IADC EAN6 EAN5 EAN4 EAN3 EAN2 EAN1 EAN0 MX2 MX1 MX0 MX2 MX1 MX0 SWDT IRCON (C0 H ) EXF2 P1ANA (90 H ) EAN7 ADCON1 (DC H ) ADCL1 ADCL0 ADCON0 (D8 H ) BD CLK BSY ADM Single / Continuous Mode Port 1 ADDAT ADST ADDATH (D9 H ) ADDATL (DA H ) (D9H) (DAH) .2 MUX .3 S&H .4 .
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C505/C505C/C505A/C505CA Interrupt System The C505 provides 12 interrupt vectors with four priority levels. Five interrupt requests can be generated by the on-chip peripherals (timer 0, timer 1, timer 2, serial interface, A/D converter). One interrupt can be generated by the CAN controller (C505C and C505CA only) or by a software setting and in this case the interrupt vector is the same. Six interrupts may be triggered externally (P3.2/ INT0, P3.3/INT1, P1.0/AN0/INT3/CC0, P1.1/AN1/INT4/CC1, P1.
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C505/C505C/C505A/C505CA Highest Priority Level P3.2 / IE0 INT0 0003 H EX0 TCON.1 Lowest Priority Level IEN0.0 IT0 TCON.0 A / D Converter IADC IRCON.0 0043 H EADC IEN1.0 Timer 0 Overflow IP1.0 IP0.0 P o l l i n g TF0 000B H ET0 TCON.5 IEN0.1 SWI >1 IRCON.1 Status S e q u e n c e 004B H ECAN ECAN IEN1.1 SIE CAN Controller Interrupt Sources CR.2 >1 Error EIE IE CR.3 CR.1 Message Transmit TXIE MCR0.5 / 4 >1 INTPND MCR0.0 / 1 Message Receive RXIE EA MCR0.3 / 2 IEN0.7 IP1.
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C505/C505C/C505A/C505CA Highest Priority Level P3.3 / IE1 INT1 TCON.3 EX1 0013 H Lowest Priority Level IEN0.2 IT1 TCON.2 P1.0 / AN0 / IEX3 IRCON.2 INT3 / CC0 EX3 0053 H IEN1.2 IP1.2 IP0.2 I3FR T2CON.6 Timer 1 Overflow TF1 TCON.7 ET1 S e q u e n c e 001B H IEN0.3 P1.1 / AN1 / INT4 / CC1 IEX4 IRCON.3 EX4 P o l l i n g 005B H IEN1.3 EA Bit addressable IP1.3 IP0.3 IEN0.
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C505/C505C/C505A/C505CA RI >1 SCON.0 USART ES TI 0023 H Lowest Priority Level IEN0.4 SCON.1 P1.2 / AN2 / INT5 / CC2 Highest Priority Level IEX5 IRCON.4 EX5 0063 H IEN1.4 Timer 2 Overflow IP1.4 IP0.4 TF2 IRCON.6 P1.5 / AN5 / T2EX EXEN2 >1 EXF2 ET2 IRCON.7 IEN0.5 S e q u e n c e 002B H IEN1.7 P1.3 / INT6 / CC3 IEX6 IRCON.5 EX6 P o l l i n g 006B H IEN1.5 EA Bit addressable IP1.5 IP0.5 IEN0.
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C505/C505C/C505A/C505CA Fail Save Mechanisms The C505 offers enhanced fail safe mechanisms, which allow an automatic recovery from software upset or hardware failure : – a programmable watchdog timer (WDT), with variable time-out period from 192 µs up to approx. 393.2 ms at 16 MHz (314.5 ms at 20 MHz).
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C505/C505C/C505A/C505CA Oscillator Watchdog The oscillator watchdog unit serves for three functions: – Monitoring of the on-chip oscillator's function The watchdog supervises the on-chip oscillator's frequency; if it is lower than the frequency of the auxiliary RC oscillator in the watchdog unit, the internal clock is supplied by the RC oscillator and the device is brought into reset; if the failure condition disappears (i.e.
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C505/C505C/C505A/C505CA EWPD (PCON1.7) WS (PCON1.4) Power - Down Mode Activated Power-Down Mode Wake - Up Interrupt P4.1 / RXDC P3.2 / INT0 Control Logic Control Logic Internal Reset Start / Stop RC Oscillator f RC 3 MHz Start / Stop XTAL1 XTAL2 10 f1 f2 Frequency Comparator On-Chip Oscillator f 2 1 IP0 (A9 H ) OWDS Int. Clock MCB03308 Figure 25 Functional Block Diagram of the Oscillator Watchdog Data Sheet 48 12.
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C505/C505C/C505A/C505CA Power Saving Modes The C505 provides two basic power saving modes, the idle mode and the power down mode. Additionally, a slow down mode is available. This power saving mode reduces the internal clock rate in normal operating mode and it can be also used for further power reduction in idle mode. – Idle mode In the idle mode the main oscillator of the C505 continues to run, but the CPU is gated off from the clock signal. All peripheral units are further provided with the clock.
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C505/C505C/C505A/C505CA OTP Memory Operation (C505A-4E and C505CA-4E only) The C505A-4E/C505CA-4E contains a 32K byte one-time programmable (OTP) program memory. With the C505A-4E/C505CA-4E fast programming cycles are achieved (1 byte in 100 µsec). Also several levels of OTP memory protection can be selected. For programming of the device, the C505A-4E/C505CA-4E must be put into the programming mode. This typically is done not in-system but in a special programming hardware.
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C505/C505C/C505A/C505CA D4 D5 D6 D7 EA / VPP N.C. PROG PSEN A7 A6 / A14 A5 / A13 Pin Configuration in Programming Mode D3 D2 D1 D0 N.C. N.C. N.C. N.C. N.C. N.C. N.C. 33 32 31 30 29 28 27 26 25 24 23 22 34 18 A4 / A12 A3 / A11 A2 / A10 A1 / A9 A0 / A8 17 VDD 40 16 41 15 42 14 43 13 VSS XTAL1 XTAL2 N.C. N.C. 35 21 36 20 37 19 C505A-4E C505CA-4E 38 39 44 2 3 4 5 6 7 8 12 9 10 11 N.C. N.C. N.C. RESET PMSEL0 N.C. PMSEL1 PSEL PRD PALE N.C.
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C505/C505C/C505A/C505CA The following Table 11 contains the functional description of all C505A-4E/C505CA-4E pins which are required for OTP memory programming. Table 11 Pin Definitions and Functions in Programming Mode Symbol Pin Number I/O Function *) RESET 4 I Reset This input must be at static “1“ (active) level during the whole programming mode. PMSEL0 PMSEL1 5 7 I I Programming mode selection pins These pins are used to select the different access modes in programming mode.
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C505/C505C/C505A/C505CA Table 11 Pin Definitions and Functions in Programming Mode (cont’d) Symbol Pin Number I/O Function *) P2.0-7 18-25 I Address lines P2.0-7 are used as multiplexed address input lines A0-A7 and A8-A14. A8-A14 must be latched with PALE. PSEN 26 I Program store enable This input must be at static “0“ level during the whole programming mode.
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C505/C505C/C505A/C505CA Basic Programming Mode Selection The basic programming mode selection scheme is shown in Figure 28. 5V VDD Clock (XTAL1/XTAL2) stable RESET “1“ PSEN “0“ 0,1 PMSEL1,0 “0“ PROG PRD “1“ PSEL “0“ PALE EA/VPP 0V During this period signals are not actively driven VPP VIH Ready for access mode selection Figure 28 Basic Programming Mode Selection Data Sheet 54 12.
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C505/C505C/C505A/C505CA Table 12 Access Modes Selection Access Mode EA/ VPP Program OTP memory byte VPP Read OTP memory byte VIH Program OTP lock bits VPP Read OTP lock bits VIH H Read OTP version byte VIH H PROG PRD PMSEL Address (Port 2) Data (Port 0) 1 0 H H H A0-7 A8-14 D0-7 H H L – D1,D0 see Table 13 L H Byte addr. of sign.
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C505/C505C/C505A/C505CA Absolute Maximum Ratings Parameter Symbol Limit Values Unit Notes min. max. TST – 65 150 °C – Voltage on VDD pins with respect VDD to ground (VSS) – 0.5 6.5 V – Voltage on any pin with respect to ground (VSS) – 0.5 VDD + 0.
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C505/C505C/C505A/C505CA Operating Conditions Parameter Symbol Supply voltage VDD Limit Values min. max. 4.25 5.5 Unit Notes V Active mode, fosc max = 20 MHz 2 Ground voltage VSS 5.5 0 Ambient temperature SAB-C505 TA 0 70 SAF-C505 TA -40 85 SAH-C505 TA -40 110 SAK-C505 TA -40 125 V PowerDown mode V Reference voltage °C – Analog reference voltage VAREF 4 VDD + 0.1 V – Analog ground voltage VAGND VSS – 0.1 VSS + 0.2 V – Analog input voltage VAIN VAGND -0.
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C505/C505C/C505A/C505CA DC Characteristics (Operating Conditions apply) Parameter Symbol Limit Values Unit Test Condition min. max. 0.2 VDD - 0.1 V 0.2 VDD - 0.3 V 0.2 VDD + 0.1 V Input low voltages all except EA, RESET EA pin RESET pin VIL VIL1 VIL2 – 0.5 – 0.5 – 0.5 Input high voltages all except XTAL1, RESET XTAL1 pin RESET pin VIH VIH1 VIH2 0.2 VDD + 0.9 VDD + 0.5 0.7 VDD VDD + 0.5 0.6 VDD VDD + 0.5 V V V – – – Output low voltages Ports 1, 2, 3, 4 Port 0, ALE, PSEN VOL VOL1 – – 0.45 0.
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C505/C505C/C505A/C505CA Power Supply Currents Parameter Symbol Limit Values 12) typ. max. Unit Test Condition 13) Active Mode 12 MHz 20 MHz IDD IDD 19.3 31.3 27.0 39 mA 7) Idle Mode 12 MHz 20 MHz IDD IDD 10.3 16.2 13.0 21.0 mA 8) Active Mode with 12 MHz slow-down enabled 20 MHz IDD IDD 3.9 4.8 5.5 7.5 mA 9) Idle Mode with 12 MHz slow-down enabled 20 MHz IDD IDD 3.2 4.0 5.0 7.0 mA 10) Power down mode IPD 10 50 µA VDD = 2..5.5 V 11) 16 MHz 20 MHz IDD IDD 28.7 35.
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C505/C505C/C505A/C505CA Note: 1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOL of ALE and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF), the noise pulse on ALE line may exceed 0.8 V.
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C505/C505C/C505A/C505CA IDD C505 C505C [mA] 40 35 30 25 t Ac ive e od M 20 A ive ct M IDD max IDD typ e od Idl od eM e de Mo e l Id 15 10 own Slow-d + e d o M Active 5 ow-down Idle Mode+Sl 4 8 12 16 20 fOSC [MHz] Figure 29 IDD Diagram of C505 and C505C C505/C505C : Power Supply Current Calculation Formulas Parameter Symbol Formula Active mode IDD typ IDD max 1.5 * fOSC + 1.3 1.5 * fOSC + 9.0 Idle mode IDD typ IDD max 0.74 * fOSC + 1.4 1.0 * fOSC + 1.
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C505/C505C/C505A/C505CA C505A-4E C505CA-4E IDD [mA] 40 35 30 t Ac 25 ive M e od IDD max IDD typ 20 Idle de Mo 15 10 ve Acti n -dow Slow + e Mod 5 wn +Slow-do Idle Mode 4 8 12 16 20 fOSC [MHz] Figure 30 IDD Diagram of C505A-4E and C505CA-4E C505A-4E/C505CA-4E : Power Supply Current Calculation Formulas Parameter Symbol Formula Active mode IDD typ IDD max 1.63 * fOSC + 2.6 1.74 * fOSC + 2.8 Idle mode IDD typ IDD max 0.69 * fOSC + 3.9 0.74 * fOSC + 4.
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C505/C505C/C505A/C505CA C505A-4R C505A-2R C505A-L C505CA-4R C505CA-2R C505CA-L IDD [mA] 40 35 30 25 20 t Ac ive M IDD max IDD typ e od Id l e Mo de 15 -down +Slow e d o M Active 10 5 Idle Mode+Slow-down 4 8 12 16 20 fOSC [MHz] Figure 31 IDD Diagram of C505A-4R/C505A-2R/C505A-L/C505CA-4R/C505CA-2R/C505CA-L C505A-4R/C505A-2R/C505A-L/C505CA-4R/C505CA-2R/C505CA-L : Power Supply Current Calculation Formulas Parameter Symbol Formula Active mode IDD typ IDD max 1.19 * fOSC + 3.77 1.
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C505/C505C/C505A/C505CA A/D Converter Characteristics of C505 and C505C (Operating Conditions apply) Parameter Symbol VAIN Analog input voltage Limit Values min. max. VAGND - VAREF + 0.2 0.
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C505/C505C/C505A/C505CA Note: 1) VAIN may exeed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these cases will be 00H or FFH, respectively. 2) During the sample time the input capacitance CAIN must be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach their final voltage level within tS.
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C505/C505C/C505A/C505CA A/D Converter Characteristics of C505A and C505CA (Operating Conditions apply) Parameter Symbol Limit Values min. max.
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C505/C505C/C505A/C505CA Note: 1) VAIN may exeed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these cases will be X000H or X3FFH, respectively. 2) During the sample time the input capacitance CAIN must be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach their final voltage level within tS.
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C505/C505C/C505A/C505CA AC Characteristics (16 MHz, 0.4 to 0.6 Duty Cycle) (Operating Conditions apply) (CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF) Program Memory Characteristics Parameter Symbol Limit Values Unit 16-MHz clock Variable Clock Duty Cycle 1/CLP= 2 MHz to 16 MHz 0.4 to 0.6 min. max. min. max.
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C505/C505C/C505A/C505CA AC Characteristics (16 MHz, 0.4 to 0.6 Duty Cycle, cont’d) External Data Memory Characteristics Parameter Symbol Limit Values 16-MHz clock Duty Cycle 0.4 to 0.6 Unit Variable Clock 1/CLP= 2 MHz to 16 MHz min. max. min. max.
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C505/C505C/C505A/C505CA AC Characteristics (16 MHz, 0.4 to 0.6 Duty Cycle, cont’d) External Clock Drive Characteristics Parameter Symbol CPU Clock = 16 MHz Duty Cycle 0.4 to 0.6 Variable CPU Clock 1/CLP = 2 to 16 MHz min. max. min. max. Unit Oscillator period CLP 62.5 62.5 62.5 500 ns High time TCLH 25 – 25 CLP - TCLL ns Low time TCLL 25 – 25 CLP - TCLH ns Rise time tR – 10 – 10 ns Fall time tF – 10 – 10 ns Oscillator duty cycle DC 0.4 0.
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C505/C505C/C505A/C505CA AC Characteristics (20 MHz, 0.5 Duty Cycle) (Operating Conditions apply) (CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF) Program Memory Characteristics Parameter Symbol Limit Values Unit 20 MHz clock Variable Clock 0.5 Duty Cycle 1/CLP = 2 MHz to 20 MHz min. max. min. max.
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C505/C505C/C505A/C505CA AC Characteristics (20 MHz, 0.5 Duty Cycle, cont’d) External Data Memory Characteristics Parameter Symbol Limit Values 20 MHz clock 0.5 Duty Cycle Unit Variable Clock 1/CLP = 2 MHz to 20 MHz min. max. min. max.
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C505/C505C/C505A/C505CA t LHLL ALE t AVLL t PLPH t LLPL t LLIV t PLIV PSEN t AZPL t PXAV t LLAX t PXIZ t PXIX Port 0 A0 - A7 Instr.IN A0 - A7 t AVIV Port 2 A8 - A15 A8 - A15 MCT00096 Figure 32 Program Memory Read Cycle Data Sheet 73 12.
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C505/C505C/C505A/C505CA t WHLH ALE PSEN t LLDV t LLWL t RLRH RD t RLDV t AVLL t RHDZ t LLAX2 t RLAZ Port 0 t RHDX A0 - A7 from Ri or DPL Data IN A0 - A7 from PCL Instr. IN t AVWL t AVDV Port 2 P2.0 - P2.7 or A8 - A15 from DPH A8 - A15 from PCH MCT00097 Figure 33 Data Memory Read Cycle Data Sheet 74 12.
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C505/C505C/C505A/C505CA t WHLH ALE PSEN t LLWL t WLWH WR t QVWX t AVLL t WHQX t LLAX2 A0 - A7 from Ri or DPL Port 0 t QVWH A0 - A7 from PCL Data OUT Instr.IN t AVWL Port 2 P2.0 - P2.7 or A8 - A15 from DPH A8 - A15 from PCH MCT00098 Figure 34 Data Memory Write Cycle tR TCL H tF 0.7V 0.7 V DD DD 0.2V - 0.1 0.2 V DD - 0.1 XTAL1 DD TCL L CLP MCT03310 Figure 35 External Clock Drive on XTAL1 Data Sheet 75 12.
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C505/C505C/C505A/C505CA AC Characteristics of Programming Mode (C505A-4E and C505CA-4E only) VDD = 5 V ± 10 %; VPP = 11.5 V ± 5 %; TA = 25 °C ± 10 °C Parameter Symbol Limit Values min. max.
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C505/C505C/C505A/C505CA t PAW PALE t PMS H, H PMSEL1,0 t PAS Port 2 t PAH A8-A14 A0-A7 D0-D7 Port 0 PROG t PWH t PCS t PWW t PCH MCT03642 Notes: PRD must be high during a programming write cycle. Figure 36 Programming Code Byte - Write Cycle Timing Data Sheet 77 12.
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C505/C505C/C505A/C505CA t PAW PALE t PMS H, H PMSEL1,0 t PAS Port 2 t PAH A8-A14 A0-A7 t PAD t PDH D0-D7 Port 0 t PRD t PDF PRD t PWH t PCS t PRW Notes: PROG must be high during a programming read cycle. t PCH MCT03643 Figure 37 Verify Code Byte - Read Cycle Timing Data Sheet 78 12.
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C505/C505C/C505A/C505CA PMSEL1,0 H, L H, L Port 0 D0, D1 D0, D1 t PCH t PCS t PMS t PMH PROG t PDH t PMS t PRD t PWW t PDF t PRW PRD t PMH MCT03644 Note: PALE should be low during a lock bit read / write cycle. Figure 38 Lock Bit Access Timing L, H PMSEL1,0 e. g. FD H Port 2 t PCH D0-7 Port 0 t PCS t PDH t PDF t PRD t PMS t PRW PRD t PMH MCT03645 Note: PROG must be high during a programming read cycle. Figure 39 Version Byte Read Timing Data Sheet 79 12.
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C505/C505C/C505A/C505CA ROM/OTP Verification Characteristics for C505 ROM Verification Mode 1 (C505(C)(A)-2R and C505(C)A-4R only) Parameter Symbol Address to valid data tAVQV Limit Values min. max. – 5 CLP P1.0 - P1.7 P2.0 - P2.6 Unit ns Address t AVQV Port 0 Data OUT Address: P1.0 - P1.7 = A0 - A7 P2.0 - P2.6 P2.5 = A8 - A14 Data: P0.0 - P0.7 = D0 - D7 Inputs:P2.6, P2.7, PSEN = V=SS Inputs: P2.7, PSEN V SS ALE, EA = V ALE, EA = V IH IH RESET = VIH2 RESET =V IH2 Note: P2.
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C505/C505C/C505A/C505CA ROM/OTP Verification Characteristics for C505 (cont’d) ROM/OTP Verification Mode 2 Parameter Symbol Limit Values Unit min. typ max. ALE pulse width tAWD – CLP – ns ALE period tACY – 6 CLP – ns Data valid after ALE tDVA – – 2 CLP ns Data stable after ALE tDSA 4 CLP – – ns P3.5 setup to ALE low tAS – tCL – ns Oscillator frequency 1/ CLP 4 – 6 MHz t ACY t AWD ALE t DSA t DVA Port 0 Data Valid t AS P3.
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C505/C505C/C505A/C505CA V DD -0.5 V 0.2 VDD +0.9 Test Points 0.2 VDD -0.1 0.45 V MCT00039 AC Inputs during testing are driven at VDD - 0.5 V for a logic ’1’ and 0.45 V for a logic ’0’. Timing measurements are made at VIHmin for a logic ’1’ and VILmax for a logic ’0’. Figure 42 AC Testing: Input, Output Waveforms VOH -0.1 V VLoad +0.1 V Timing Reference Points VLoad VLoad -0.1 V VOL +0.
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C505/C505C/C505A/C505CA GPM05622 P-MQFP-44-2 (SMD) (Plastic Metric Quad Flat Package) Figure 45 P-MQFP-44 Package Outline Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information” SMD = Surface Mounted Device Data Sheet 83 Dimensions in mm 12.
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