D a ta S he e t , F e b . 20 0 3 C515C 8 - B i t S i n gl e - C h i p M i c r o c o nt r o l l e r M i c r o c o n t r o l l er s N e v e r s t o p t h i n k i n g .
Edition 2003-02 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 München, Germany © Infineon Technologies AG 2003. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved.
D a ta S he e t , F e b . 20 0 3 C515C 8 - B i t S i n gl e - C h i p M i c r o c o nt r o l l e r M i c r o c o n t r o l l er s N e v e r s t o p t h i n k i n g .
C515C Data Sheet Revision History: 2003-02 Previous Version: 2000-08 Page Subjects (major changes since last revision) Enhanced Hooks Technology™ is a trademark of Infineon Technologies. We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.
8-Bit Single-Chip Microcontroller C515C Features • Full upward compatibility with SAB 80C515A • On-chip program memory (with optional memory protection) – C515C-8R 64 Kbytes on-chip ROM – C515C-8E 64 Kbytes on-chip OTP – alternatively up to 64 Kbytes external program memory • 256 bytes on-chip RAM • 2 Kbytes of on-chip XRAM • Up to 64 Kbytes external data memory • Superset of the 8051 architecture with 8 datapointers • Up to 10 MHz external operating frequency (1 µs instruction cycle time at 6 MHz externa
C515C • Eight ports: 48 + 1 digital I/O lines, 8 analog inputs – Quasi-bidirectional port structure (8051 compatible) – Port 5 selectable for bidirectional port structure (CMOS voltage levels) • Full-CAN controller on-chip – 256 register/data bytes are located in external data memory area – max.
C515C The C515C-8R contains a non-volatile 64 Kbytes read-only program memory. The C515C-L is identical to the C515C-8R, except that it lacks the on-chip program memory. The C515C-8E is the OTP version in the C515C microcontroller with an on-chip 64 Kbytes one-time programmable (OTP) program memory. The C515C is mounted in a P-MQFP-80-1 package.
C515C VAGND VAREF Port 0 8 Bit Digital I/O Port 1 8 Bit Digital I/O XTAL1 XTAL2 Port 2 8 Bit Digital I/O ALE PSEN EA RESET PE/SWD HWPD CPUR Port 3 8 Bit Digital I/O Port 4 8 Bit Digital I/O C515C Port 5 8 Bit Digital I/O Port 6 8 Bit Analog/ Digital Inputs VSSE1 VDDE1 VSSE2 VDDE2 Port 7 1 Bit Digital I/O VSS1 VDD1 VSSCLK VDDCLK VSSEXT VDDEXT MCL02714 Figure 2 Data Sheet Logic Symbol 4 2003-02
P5.7 P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VSSEXT VDDEXT EA ALE PSEN CPUR P2.7/A15 P2.6/A14 P2.5/A13 P2.4/A12 P2.3/A11 C515C 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P5.6 P5.5 P5.4 P5.3 P5.2 P5.1 P5.0 VDDE2 HWPD VSSE2 N.C. P4.0/ADST P4.1/SCLK P4.2/SRI PE/SWD P4.3/STO P4.4/SLS P4.5/INT8 P4.6/TXDC P4.7/RXDC 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 C515C 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 P2.2/A10 P2.1/A9 P2.
C515C Table 2 Symbol Pin Definitions and Functions Pin Number I/O1) Function P-MQFP-80-1 RESET 1 I RESET A low level on this pin for the duration of two machine cycles while the oscillator is running resets the C515C. A small internal pullup resistor permits power-on reset using only a capacitor connected to VSS . VAREF VAGND 3 – Reference voltage for the A/D converter 4 – Reference ground for the A/D converter P6.0-P6.
C515C Table 2 Symbol Pin Definitions and Functions (cont’d) Pin Number I/O1) Function P-MQFP-80-1 P3.0-P3.7 15-22 15 16 17 18 19 20 21 22 Data Sheet I/O Port 3 is an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 3 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs.
C515C Table 2 Symbol Pin Definitions and Functions (cont’d) Pin Number I/O1) Function P-MQFP-80-1 P1.0 - P1.7 31-24 I/O Port 1 is an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 1 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 1 pins being externally pulled low will source current (IIL, in the DC characteristics) because of the internal pullup resistors.
C515C Table 2 Symbol Pin Definitions and Functions (cont’d) Pin Number I/O1) Function P-MQFP-80-1 XTAL1 37 O XTAL1 Output of the inverting oscillator amplifier. P2.0-P2.7 38-45 I/O Port 2 is an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 2 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs.
C515C Table 2 Symbol Pin Definitions and Functions (cont’d) Pin Number I/O1) Function P-MQFP-80-1 ALE 48 O The Address Latch Enable output is used for latching the address into external memory during normal operation. It is activated every six oscillator periods, except during an external data memory access. ALE can be switched off when the program is executed internally. EA 49 I External Access Enable When held high, the C515C executes instructions always from the internal ROM.
C515C Table 2 Symbol Pin Definitions and Functions (cont’d) Pin Number I/O1) Function P-MQFP-80-1 HWPD 69 I Hardware Power Down A low level on this pin for the duration of one machine cycle while the oscillator is running resets the C515C. A low level for a longer period will force the part to power down mode with the pins floating. P4.0-P4.7 72-74, 76-80 I/O Port 4 is an 8-bit quasi-bidirectional I/O port with internal pull-up resistors.
C515C Table 2 Symbol Pin Definitions and Functions (cont’d) Pin Number I/O1) Function P-MQFP-80-1 PE/SWD 75 I Power saving mode enable / Start watchdog timer A low level on this pin allows the software to enter the power down, idle and slow down mode. In case the low level is also seen during reset, the watchdog timer function is off on default. Use of the software controlled power saving modes is blocked, when this pin is held on high level.
C515C Table 2 Symbol Pin Definitions and Functions (cont’d) Pin Number I/O1) Function P-MQFP-80-1 VDDEXT 50 – Supply voltage for external access pins This pin is used for power supply of the I/O ports and control signals which are used during external accesses (for Port 0, Port 2, ALE, PSEN, P3.6/WR, and P3.7/RD).
C515C Oscillator Watchdog XRAM 2k x 8 XTAL1 XTAL2 RAM 256 x 8 ROM/OTP 64k x 8 Multiple V DD /V SS Lines OSC & Timing ALE CPU PSEN 8 Datapointers EA CPUR Emulation Support Logic Programmable Watchdog Timer PE/SWD HWPD Timer 0 Port 0 Port 0 8 Bit Digital I/O Port 1 Port 1 8 Bit Digital I/O Capture Compare Unit Port 2 Port 2 8 Bit Digital I/O USART Port 3 Port 3 8 Bit Digital I/O Port 4 Port 4 8 Bit Digital I/O Port 5 Port 5 8 Bit Digital I/O Port 6 Port 6 8 Bit Analog/ Digital In
C515C CPU The C515C is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44% one-byte, 41% two-byte, and 15% three-byte instructions. With a 6 MHz crystal, 58% of the instructions are executed in 1 µs (10 MHz: 600 ns). PSW Special Function Register (D0H) Reset Value: 00H Bit No.
C515C Memory Organization The C515C CPU manipulates data and operands in the following five address spaces: • • • • • • up to 64 Kbytes of internal/external program memory up to 64 Kbytes of external data memory 256 bytes of internal data memory 256 bytes CAN controller registers / data memory 2 Kbytes of internal XRAM data memory a 128 byte special function register area Figure 5 illustrates the memory address spaces of the C515C.
C515C Control of XRAM/CAN Controller Access The XRAM in the C515C is a memory area that is logically located at the upper end of the external memory space, but is integrated on the chip. Because the XRAM and the CAN controller is used in the same way as external data memory the same instruction types (MOVX) must be used for accessing the XRAM. Two bits in SFR SYSCON, XMAP0 and XMAP1, control the accesses to the XRAM and the CAN controller. SYSCON Special Function Register Bit No.
C515C The XRAM/CAN controller can be accessed by read/write instructions (MOVX A,DPTR, MOVX @DPTR,A), which use the 16-bit DPTR for indirect addressing. For accessing the XRAM or CAN controller, the effective address stored in DPTR must be in the range of F700H to FFFFH. The XRAM can be also accessed by read/write instructions (MOVX A,@Ri, MOVX @Ri,A), which use only an 8-bit address (indirect addressing with registers R0 or R1).
C515C Table 3 Behaviour of P0/P2 and RD/WR During MOVX Accesses XMAP1, XMAP0 EA = 0 MOVX @DPTR MOVX @ Ri EA = 1 MOVX @DPTR MOVX @ Ri 00 10 X1 DPTR < XRAM/CAN address range a) P0/P2→Bus b) RD/WR active c) ext.memory is used a) P0/P2→Bus b) RD/WR active c) ext.memory is used a) P0/P2→Bus b) RD/WR active c) ext.
C515C Reset and System Clock The reset input is an active low input at pin RESET. Since the reset is synchronized internally, the RESET pin must be held low for at least two machine cycles (12 oscillator periods) while the oscillator is running. A pullup resistor is internally connected to VDD to allow a power-up reset with an external capacitor only. An automatic reset can be obtained when VDD is applied by connecting the RESET pin to VSS via a capacitor. Figure 6 shows the possible reset circuitries.
C515C Crystal/Resonator Oscillator Mode Driving from External Source C N.C. XTAL1 XTAL1 2 - 10 MHz External Oscillator Signal C XTAL2 Crystal Mode : C = 20 pF ± 10 pF (incl. stray capacitance) Resonator Mode : C = depends on selected ceramic resonator Figure 7 XTAL2 MCT02765 Recommended Oscillator Circuitries Multiple Datapointers As a functional enhancement to the standard 8051 architecture, the C515C contains eight 16-bit datapointers instead of only one datapointer.
C515C Enhanced Hooks Emulation Concept The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative way to control the execution of C500 MCUs and to gain extensive information on the internal operation of the controllers. Emulation of on-chip ROM based programs is possible, too. Each production chip has built-in logic for the support of the Enhanced Hooks Emulation Concept. Therefore, no costly bond-out chips are necessary for emulation.
C515C Special Function Registers The registers, except the program counter and the four general purpose register banks, reside in the special function register area. The special function register area consists of two portions: the standard special function register area and the mapped special function register area. Two special function registers of the C515C (PCON1 and DIR5) are located in the mapped special function register area.
C515C Table 4 Special Function Registers - Functional Block Block Symbol Name Addr Contents after Reset CPU ACC B DPH DPL DPSEL PSW SP SYSCON1) Accumulator B-Register Data Pointer, High Byte Data Pointer, Low Byte Data Pointer Select Register Program Status Word Register Stack Pointer System Control Register C515C-8R C515C-8E E0H2) F0H2) 83H 82H 92H D0H2) 81H B1H B1H 00H 00H 00H 00H XXXXX000B3) 00H 07H X010XX01B3) X010X001B3) A/DConverter ADCON01) ADCON1 ADDATH ADDATL A/D Converter Control Re
C515C Table 4 Special Function Registers - Functional Block (cont’d) Block Symbol Name Addr Contents after Reset Serial Channel ADCON01) PCON1) SBUF SCON SRELL SRELH A/D Converter Control Register 0 Power Control Register Serial Channel Buffer Register Serial Channel Control Register Serial Channel Reload Register, low byte Serial Channel Reload Register, high byte D8H2) 87H 99H 98H2) AAH BAH 00H 00H XXH3) 00H D9H XXXXXX11B3) CAN Controller CR SR IR BTR0 BTR1 GMS0 GMS1 UGML0 UGML1 LGML0 LGML1
C515C Table 4 Special Function Registers - Functional Block (cont’d) Block Symbol Name Addr Contents after Reset SSC Interface SSCCON STB SRB SCF SCIEN SSCMOD SSC Control Register SSC Transmit Buffer SSC Receive Register SSC Flag Register SSC Interrupt Enable Register SSC Mode Test Register 93H2) 94H 95H ABH2) ACH 96H 07H XXH3) XXH3) XXXXXX00B3) XXXXXX00B3) 00H Timer 0/ Timer 1 TCON TH0 TH1 TL0 TL1 TMOD Timer 0/1 Control Register Timer 0, High Byte Timer 1, High Byte Timer 0, Low Byte Timer 1
C515C Table 5 Contents of the SFRs, SFRs in Numeric Order of their Addresses Addr. Register Content Bit 7 after Reset1) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 80H2) P0 FFH .7 .6 .5 .4 .3 .2 .1 .0 81H SP 07H .7 .6 .5 .4 .3 .2 .1 .0 82H DPL 00H .7 .6 .5 .4 .3 .2 .1 .0 83H DPH 00H .7 .6 .5 .4 .3 .2 .1 .0 86H WDTREL 00H WDT PSEL .6 .5 .4 .3 .2 .1 .
C515C Table 5 Contents of the SFRs, SFRs in Numeric Order of their Addresses (cont’d) Addr. Register Content Bit 7 after Reset1) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 AAH SRELL D9H .7 .6 .5 .4 .3 .2 .1 .
C515C Table 5 Contents of the SFRs, SFRs in Numeric Order of their Addresses (cont’d) Addr. Register Content Bit 7 after Reset1) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 D0H2) PSW 00H CY AC F0 RS1 RS0 OV F1 P D8H2) ADCON0 00H BD CLK ADEX BSY ADM MX2 MX1 MX0 D9H ADDATH 00H .9 .8 .7 .6 .5 .4 .3 .2 DAH ADDATL 00XXXXXXB .1 .0 – – – – – – DBH P6 – .7 .6 .5 .4 .3 .2 .1 .0 DCH ADCON1 0XXXX000B ADCL – – – 0 MX2 MX1 MX0 E0H2) ACC 00H .
C515C Table 6 Contents of the CAN Registers in Numeric Order of their Addresses Addr. Regis1) n = 1 to FH ter Content Bit 7 after Reset2) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 EIE SIE IE INIT RXOK TXOK LEC2 LEC1 LEC0 F700H CR 01H TEST CCE F701H SR XXH BOFF EWRN – F702H IR XXH F704H BTR0 UUH F705H BTR1 0UUU. UUUUB F706H GMS0 UUH F707H GMS1 UUU1. 1111B F708H ID28-21 F709H UGML0 UUH UGML1 UUH F70AH LGML0 UUH ID12-5 F70BH LGML1 UUUU.
C515C Table 6 Contents of the CAN Registers in Numeric Order of their Addresses (cont’d) Addr. Regis1) n = 1 to FH ter Content Bit 7 after Reset2) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 F7nCH DB5n XXH .7 .6 .5 .4 .3 .2 .1 .0 F7nDH DB6n XXH .7 .6 .5 .4 .3 .2 .1 .0 F7nEH DB7n XXH .7 .6 .5 .4 .3 .2 .1 .0 1) The notation “n” in the address definition defines the number of the related message object.
C515C Digital I/O Ports The C515C allows for digital I/O on 49 lines grouped into 6 bidirectional 8-bit ports and one 1-bit port. Each port bit consists of a latch, an output driver and an input buffer. Read and write accesses to the I/O ports P0 through P7 are performed via their corresponding special function registers P0 to P7.
C515C Port Structure Selection of Port 5 After a reset operation of the C515C, the quasi-bidirectional 8051-compatible port structure is selected. For selection of the bidirectional (CMOS) port 5 structure the bit PMOD of SFR SYSCON must be set. Because each port 5 pin can be programmed as an input or an output, additionally, after the selection of the bidirectional mode the direction register DIR5 of port 5 must be written. This direction register is mapped to the port 5 register.
C515C Timer / Counter 0 and 1 Timer / Counter 0 and 1 can be used in four operating modes as listed in Table 7: Table 7 Mode Timer/Counter 0 and 1 Operating Modes Description TMOD Timer/Counter Input Clock M1 M0 internal external (max) 0 8-bit timer/counter with a divide-by-32 prescaler 0 0 fOSC/6 × 32 fOSC/12 × 32 1 16-bit timer/counter 0 1 fOSC/6 fOSC/12 2 8-bit timer/counter with 8-bit 1 autoreload 0 3 Timer/counter 0 used as one 8-bit timer/counter and one 8-bit timer / Timer 1
C515C Timer / Counter 2 with Compare/Capture/Reload The timer 2 of the C515C provides additional compare/capture/reload features, which allow the selection of the following operating modes: • Compare: up to 4 PWM signals with 16-bit/600 ns resolution • Capture: up to 4 high speed capture inputs with 600 ns resolution • Reload: modulation of timer 2 cycle time The block diagram in Figure 12 shows the general configuration of timer 2 with the additional compare/capture/reload registers.
C515C Timer 2 Operating Modes The timer 2, which is a 16-bit-wide register, can operate as timer, event counter, or gated timer. A roll-over of the count value in TL2/TH2 from all 1’s to all 0’s sets the timer overflow flag TF2 in SFR IRCON, which can generate an interrupt. The bits in register T2CON are used to control the timer 2 operation. Timer Mode: In timer function, the count rate is derived from the oscillator frequency.
C515C Timer 2 Compare Modes The compare function of a timer/register combination operates as follows: the 16-bit value stored in a compare or compare/capture register is compared with the contents of the timer register; if the count value in the timer register matches the stored value, an appropriate output signal is generated at a corresponding port pin and an interrupt can be generated.
C515C Compare Mode 1 If compare mode 1 is enabled and the software writes to the appropriate output latch at the port, the new value will not appear at the output pin until the next compare match occurs. Thus, it can be choosen whether the output signal has to make a new transition (1-to-0 or 0-to-1, depending on the actual pin-level) or should keep its old value at the time when the timer value matches the stored compare value.
C515C Serial Interface (USART) The serial port is full duplex and can operate in four modes (one synchronous mode, three asynchronous modes) as illustrated in Table 8.
C515C Timer 1 Overflow f OSC ADCON0.7 (BD) Baud Rate Generator Mode 1 Mode 3 0 1 SCON.7 SCON.6 (SM0/ SM1) PCON.7 (SMOD) ÷2 0 1 (SRELH SRELL) Baud Rate Clock Mode 2 Only one mode can be selected Mode 0 ÷6 Note: The switch configuration shows the reset state. Figure 15 MCS02733 Block Diagram of Baud Rate Generation for the Serial Interface Table 9 below lists the values/formulas for the baud rate calculation of the serial interface with its dependencies of the control bits BD and SMOD.
C515C SSC Interface The C515C microcontroller provides a Synchronous Serial Channel unit, the SSC. This interface is compatible to the popular SPI serial bus interface. Figure 16 shows the block diagram of the SSC. The central element of the SSC is an 8-bit shift register. The input and the output of this shift register are each connected via a control logic to the pin P4.2 / SRI (SSC Receiver In) and P4.3 / STO (SSC Transmitter Out).
C515C CAN Controller The on-chip CAN controller is the functional heart which provides all resources that are required to run the standard CAN protocol (11-bit identifiers) as well as the extended CAN protocol (29-bit identifiers). It provides a sophisticated object layer to relieve the CPU of as much overhead as possible when controlling many different message objects (up to 15). This includes bus arbitration, resending of garbled messages, error handling, interrupt generation, etc.
C515C TXDC RXDC BTL-Configuration CRC Gen.
C515C The Cyclic Redundancy Check Register (CRC) generates the Cyclic Redundancy Check code to be transmitted after the data bytes and checks the CRC code of incoming messages. This is done by dividing the data stream by the code generator polynomial. The Error Management Logic (EML) is responsible for the fault confinement of the CAN device. Its counters, the Receive Error Counter and the Transmit Error Counter, are incremented and decremented by commands from the Bit Stream Processor.
C515C 10-Bit A/D Converter The C515C includes a high performance / high speed 10-bit A/D-Converter (ADC) with 8 analog input channels. It operates with a successive approximation technique and uses self calibration mechanisms for reduction and compensation of offset and linearity errors.
C515C ADCL f OSC ÷4 Conversion Clock f ADC MUX ÷8 A/D Converter Clock Prescaler Conditions: Figure 18 Data Sheet Input Clock f IN f ADC max <_ 2 MHz f IN = f OSC = 1 CLP MCU System Clock Rate (fOSC) ADCL Conversion Clock fADC [MHz] 2 MHz 0 .5 4 MHz 0 1 6 MHz 0 1.5 8 MHz 0 2 10 MHz 1 1.
C515C Internal Bus IEN1 (B8 H) EXEN2 SWDT EX6 EX5 EX4 EX3 EX2 EADC TF2 IEX6 IEX5 IEX4 IEX3 IEX2 IADC P6.6 P6.5 P6.4 P6.3 P6.2 P6.1 P6.0 - - - MX2 MX1 MX0 ADEX BSY ADM MX2 MX1 MX0 IRCON (C0 H) EXF2 P6 (DB H ) P6.7 ADCON1 (DC H ) ADCL - ADCON0 (D8 H) BD CLK Single/ Continuous Mode Port 6 MUX S&H A/D Converter Conversion Clock Prescaler f OSC Conversion Clock f ADC Input Clock f IN VAREF VAGND P4.
C515C Interrupt System The C515C provides 17 interrupt sources with four priority levels. Seven interrupts can be generated by the on-chip peripherals (timer 0, timer 1, timer 2, serial interface, A/D converter, SSC interface, CAN controller), and ten interrupts may be triggered externally (P1.5/T2EX, P3.2/INT0, P3.3/INT1, P1.4/INT2, P1.0/INT3, P1.1/INT4, P1.2/INT5, P1.3/INT6, P7.0/INT7, P4.5/INT8).
C515C Highest Priority Level P3.2/ INT0 IE0 TCON.1 IT0 TCON.0 A/D Converter IADC IRCON.0 Timer 0 Overflow TF0 TCON.5 EX0 IEN0.0 0003 H EADC IEN1.0 0043 H Lowest Priority Level ET0 IEN0.1 000B H ECAN IEN2.1 008B H EX2 IEN1.1 004B H IP1.0 IP0.0 IP1.1 IP0.1 SIE CR.2 Polling Sequence CAN Controller Interrupt Sources Status <_1 IE CR.1 Error EIE CR.3 Message Transmit Message Receive see Note TXIE MCR0.3/2 <_ 1 INTPND MCR0.0/1 RXIE MCR0.5/4 P1.4/ INT2 I2FR T2CON.
C515C Highest Priority Level IE1 TCON.3 IT1 TCON.2 SSC Inerface WCOL SCF.1 TC SCF.0 P1.0/ INT3/ CC0 WCEN SCIEN.1 Timer 1 Overflow ESSC IEN2.2 IEX3 IRCON.2 TF1 TCON.7 P1.1/ INT4/ CC1 IEX4 IRCON.3 Bit addressable 0013 H Lowest Priority Level <_ 1 TCEN SCIEN.0 I3FR T2CON.6 EX1 IEN0.2 EX3 IEN1.2 ET1 IEN0.3 EX4 IEN1.3 0093 H 0053 H Data Sheet IP0.2 IP1.3 IP0.3 001B H 005B H EAL IEN0.7 Request Flag is cleared by hardware Figure 21 IP1.2 Polling Sequence P3.
C515C USART Highest Priority Level <_ 1 TI SCON.1 0023 H ES IEN0.4 Lowest Priority Level P7.0/ INT7 00A3 H EX7 IEN2.4 P1.2/ INT5/ CC2 IEX5 IRCON.4 Timer 2 Overflow TF2 IRCON.6 P1.5/ T2EX EXEN2 IEN1.7 P4.5/ INT8 0063 H EX5 IEN1.4 IEX6 IRCON.5 IP0.5 00AB H 006B H EX6 IEN1.5 EAL IEN0.7 Bit addressable Request Flag is cleared by hardware Data Sheet IP1.5 002B H ET2 IEN0.5 EX8 IEN2.5 Figure 22 IP0.4 <_ 1 EXF2 IRCON.7 P1.3/ INT6/ CC3 IP1.4 Polling Sequence RI SCON.
C515C Table 10 Interrupt Source and Vectors Interrupt Source Interrupt Vector Address Interrupt Request Flags External Interrupt 0 0003H IE0 Timer 0 Overflow 000BH TF0 External Interrupt 1 0013H IE1 Timer 1 Overflow 001BH TF1 Serial Channel 0023H RI / TI Timer 2 Overflow / Ext.
C515C Fail Save Mechanisms The C515C offers two on-chip peripherals which monitor the program flow and ensure an automatic “fail-safe” reaction for cases where the controller’s hardware fails or the software hangs up: • A programmable watchdog timer (WDT) with variable time-out period from 512 microseconds up to approx. 1.1 seconds at 6 MHz.
C515C two consecutive instructions which set the bits WDT and SWDT each. The reset cause (external reset or reset caused by the watchdog) can be examined by software (flag WDTS). It must be noted, however, that the watchdog timer is halted during the idle mode and power down mode of the processor.
C515C EWPD (PCON1.7) P3.
C515C Power Saving Modes The C515C provides two basic power saving modes, the idle mode and the power down mode. Additionally, a slow down mode is available. This power saving mode reduces the internal clock rate in normal operating mode and it can be also used for further power reduction in idle mode. • Idle mode The CPU is gated off from the oscillator. All peripherals are still provided with the clock and are able to work. Idle mode is entered by software and can be left by an interrupt or reset.
C515C Table 11 Power Saving Modes Overview Mode Entering (2-Instruction Example) Leaving by Idle mode ORL PCON, #01H Occurrence of an ORL PCON, #20H interrupt from a peripheral unit Hardware Reset Remarks CPU clock is stopped; CPU maintains their data; peripheral units are active (if enabled) and provided with clock Software Power-Down Mode ORL PCON, #02H Hardware Reset ORL PCON, #40H Short low pulse at pin P3.2/INT0 (or P4.
C515C OTP Memory Operation (C515C-8E only) The C515C-8E contains a 64 Kbytes one-time programmable (OTP) program memory. With the C515C-8E fast programming cycles are achieved (1 byte in 100 µs). Also several levels of OTP memory protection can be selected. For programming of the device, the C515C-8E must be put into the programming mode. This typically is done not in-system but in a special programming hardware.
C515C N.C. D7 D6 D5 D4 D3 D2 D1 D0 VSS VDD EA/VPP PROG PSEN N.C. A7/A15 A6/A14 A5/A13 A4/A12 A3/A11 C515C-8E Pin Configuration in Programming Mode 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 N.C. N.C. N.C. N.C. N.C. N.C. N.C. VDD N.C. VSS N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 C515C-8E 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 A2/A10 A1/A9 A0/A8 XTAL1 XTAL2 VSS VSS VDD VDD N.C. N.C. N.C. N.C. N.C.
C515C The following Table 12 contains the functional description of all C515C-8E pins which are required for OTP memory programming. Table 12 Pin Definitions and Functions in Programming Mode Symbol Pin Number I/O1) Function RESET 1 PMSEL0 15 PMSEL1 16 I Reset This input must be at static “0” (active) level during the whole programming mode. I I Programming mode selection pins These pins are used to select the different access modes in programming mode.
C515C Table 12 Pin Definitions and Functions in Programming Mode (cont’d) Symbol Pin Number I/O1) Function A0/A8 A7/A15 38 - 45 I Address lines P2.0-7 are used as multiplexed address input lines A0-A7 and A8-A15. A8-A15 must be latched with PALE. PSEN 47 I Program store enable This input must be at static “0” level during the whole programming mode.
C515C C515C-8E Basic Programming Mode Selection The basic programming mode selection scheme is shown in Figure 27. 5V VDD Clock (XTAL1/XTAL2) Stable RESET "0" PSEN "0" 0.
C515C Table 13 Access Modes Selection Access Mode EA/ PROG PRD VPP PMSEL 1 0 Address (Port 2) Data (Port 0) Program OTP memory byte VPP H H H A0-7 A8-15 D0-7 Read OTP memory byte H H L – Read OTP lock bits VIH H VPP VIH H D1, D0 see Table 14 Read OTP version byte VIH L H Byte addr.
C515C Table 14 Lock Bit Protection Types Lock Bits at D1, D0 Protection Protection Type Level D1 D0 1 1 Level 0 The OTP lock feature is disabled. During normal operation of the C515C-8E, the state of the EA pin is not latched on reset. 1 0 Level 1 During normal operation of the C515C-8E, MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory. EA is sampled and latched on reset.
C515C Absolute Maximum Ratings Parameter Symbol Limit Values Unit Notes min. max. -65 150 °C – -0.5 6.5 V – Voltage on any pin with respect VIN to ground (VSS) -0.5 VDD + 0.
C515C Operating Conditions Parameter Supply voltage Ground voltage Symbol VDD Limit Values min. max. 4.25 5.5 V Active mode, fOSCmax = 10 MHz 2 5.5 V Power Down mode V Reference voltage °C – VSS 0 Ambient temperature: TA TA SAF-C505 TA SAH-C505 Analog reference voltage VAREF VAGND Analog ground voltage Analog input voltage VAIN fOSC XTAL clock SAB-C515C Data Sheet Unit Notes 0 70 -40 85 -40 110 4 VSS - 0.1 VAGND VDD + 0.1 V VSS + 0.
C515C DC Characteristics (Operating Conditions apply) Parameter Input low voltages all except EA, RESET, HWPD EA pin RESET and HWPD pins Port 5 in CMOS mode Input high voltages all except XTAL2, RESET, and HWPD) XTAL2 pin RESET and HWPD pins Port 5 in CMOS mode Symbol min. VIL VIL1 VIL2 VILC VIH VIH1 VIH2 VIHC Output low voltages Ports 1, 2, 3, 4, 5, 7 (incl. CMOS) VOL Port 0, ALE, PSEN, CPUR VOL1 P4.1, P4.3 in push-pull mode VOL3 Output high voltages Ports 1, 2, 3, 4, 5, 7 Limit Values max.
C515C 1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOL of ALE and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF), the noise pulse on ALE line may exceed 0.8 V. In such cases it may be desirable to qualify ALE with a Schmitt-trigger, or use an address latch with a Schmitt-trigger strobe input.
C515C Power Supply Current Parameter Sym- Limit Values Unit Test Condition bol typ.1) max.2) C515C-8R/ 6 MHz IDD C515C-LM 10 MHz 11.97 18.81 13.74 21.10 mA 6 MHz IDD 10 MHz 11.3 17.66 12.94 20.10 mA C515C-8R/ 6 MHz IDD C515C-LM 10 MHz 6.9 10.46 7.87 11.87 mA 6 MHz IDD 10 MHz 3.95 4.71 4.70 5.50 mA Active mode C515C-8R/ 6 MHz IDD with slow-down C515C-LM 10 MHz enabled C515C-8E 6 MHz IDD 10 MHz 4.06 4.62 5.03 5.75 mA 4.01 4.65 4.77 5.53 mA C515C-8R/ 6 MHz IDD C515C-LM 10 MHz 3.54 3.
C515C 6) IDD (idle mode with slow-down mode) is measured with all output pins disconnected and with all peripherals disabled; XTAL2 driven with tCLCH, tCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VDD - 0.5 V; XTAL1 = N.C.; RESET = VDD; EA = VSS; Port0 = VDD; all other pins are disconnected; the microcontroller is put into idle mode with slow-down enabled by software. 7) IPD (power-down mode) is measured under following conditions: EA = RESET = Port 0 = Port 6 = VDD; XTAL1 = N.C.
C515C Power Supply Current Calculation Formulas Parameter Active mode C515C-8R/ C515C-LM C515C-8E Idle mode C515C-8R/ C515C-LM C515C-8E Active mode with slow-down enabled C515C-8R/ C515C-LM C515C-8E Idle mode with slow-down enabled C515C-8R/ C515C-LM C515C-8E Symbol Formula IDD typ IDD max IDD typ IDD max IDD typ IDD max IDD typ IDD max IDD typ IDD max IDD typ IDD max IDD typ IDD max IDD typ IDD max 1.71 × fOSC + 1.71 1.84 × fOSC + 2.7 1.59 × fOSC + 1.76 1.79 × fOSC + 2.2 0.89 × fOSC + 1.56 1.
C515C [mA] C515C-8E C515C-LM 25 20 eM od e 15 Ac ti v e M od e Ac tiv IDD max IDD typ 10 le Id M e od eM Idl o own M Slow-d e od de 5 Idle+Slow-down fOSC 2 Figure 28 Data Sheet 4 6 8 10 [MHz] IDD Diagrams of C515C-8R/C515C-LM 72 2003-02
C515C C515C-8E [mA] 25 Ac tiv e M od e 20 15 IDD max IDD typ 10 Slow Mode+ e v ti c A -down Idle M ode 5 Idle Mode+Slow-down fOSC 2 Figure 29 Data Sheet 4 6 8 10 [MHz] IDD Diagrams of C515C-8E 73 2003-02
C515C A/D Converter Characteristics (Operating Conditions apply) Parameter Symbol Limit Values Unit Test Condition min. max.
C515C Clock Calculation Table tADC 8 × tIN 4 × tIN Clock Prescaler Ratio ADCL ÷8 1 ÷4 0 Further timing conditions: tADC min = 500 ns tIN = 1 / fOSC = tCLP Data Sheet 75 tS 16 × tIN 8 × tIN tADCC 96 × tIN 48 × tIN 2003-02
C515C AC Characteristics (Operating Conditions apply) (CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF) Program Memory Characteristics Parameter Symbol Limit Values Unit Variable Clock 1/CLP = 2 MHz to 10 MHz 10-MHz Clock Duty Cycle 0.4 to 0.6 min. max. min. max.
C515C External Data Memory Characteristics Parameter Symbol Limit Values 10-MHz Clock Duty Cycle 0.4 to 0.6 Unit Variable Clock 1/CLP= 2 MHz to 10 MHz min. max. min. max.
C515C SSC Interface Characteristics Parameter Symbol Clock Cycle Time: Master Mode Slave Mode tSCLK tSCLK tSCH tSCL tD tHO tS tHI tDTC Clock high time Clock low time Data output delay Data output hold Data input setup Data input hold TC bit set delay Limit Values Unit min. max. 0.4 1.0 – – µs µs 360 – ns 360 – ns – 100 ns 0 – ns 100 – ns 100 – ns – 8 CLP ns External Clock Drive at XTAL2 Parameter Symbol CPU Clock = 10 MHz Duty cycle 0.4 to 0.
C515C t LHLL ALE t AVLL t PLPH t LLPL t LLIV t PLIV PSEN t AZPL t PXAV t LLAX t PXIZ t PXIX Port 0 A0 - A7 Instr.
C515C t WHLH ALE PSEN t LLDV t LLWL t RLRH RD t RLDV t AVLL t RHDZ t LLAX2 t RLAZ Port 0 t RHDX A0 - A7 from Ri or DPL Data IN A0 - A7 from PCL Instr. IN t AVWL t AVDV Port 2 P2.0 - P2.
C515C t WHLH ALE PSEN t LLWL t WLWH WR t QVWX t AVLL t WHQX t LLAX2 A0 - A7 from Ri or DPL Port 0 t QVWH A0 - A7 from PCL Data OUT Instr.IN t AVWL Port 2 P2.0 - P2.
C515C t SCLK t SCL t SCH ~ ~ SCLK t HD ~ ~ tD MSB LSB ~ ~ STO t HI ~ ~ tS MSB LSB ~ ~ SRI t DTC ~ ~ TC MCT02417 Figure 34 SSC Timing Notes: 1. Shown is the data/clock relationship for CPOL = CPHA = 1. The timing diagram is valid for the other cases accordingly. 2. In the case of slave mode and CPHA = 0, the output delay for the MSB applies to the falling edge of SLS (if transmitter is enabled). 3.
C515C OTP Memory Programming Mode Characteristics VDD = 5 V ± 10%; VPP = 11.5 V ± 5%; TA = 25 °C ± 10 °C Parameter Symbol Limit Values Unit min. max.
C515C t PAW PALE t PMS H, H PMSEL1,0 t PAS Port 2 t PAH A8-15 A0-7 D0-7 Port 0 PROG t PWH t PCS t PWW Notes: PRD must be high during a programming write cycle.
C515C t PAW PALE t PMS H, H PMSEL1,0 t PAS Port 2 t PAH A8-15 A0-7 t PAD t PDH D0-7 Port 0 t PRD t PDF PRD t PWH t PCS t PRW Notes: PROG must be high during a programming read cycle.
C515C PMSEL1,0 H, L Port 0 D0, D1 H, L D0, D1 t PCH t PCS t PMS t PMH PROG t PDH t PMS t PRD t PWW t PDF t PRW t PMH PRD Note: PALE should be low during a lock bit read / write cycle.
C515C L, H PMSEL1,0 e. g. FD H Port 2 t PCH D0-7 Port 0 t PCS t PDH t PDF t PRD t PMS t PRW PRD t PMH Note: PROG must be high during a programming read cycle.
C515C ROM/OTP Verification Characteristics for C515C-8R / C515C-8E ROM Verification Mode 1 (C515C-8R) Parameter Symbol Address to valid data P1.0 - P1.7 P2.0 - P2.7 tAVQV Limit Values min. max. – 5 CLP Address Unit ns New Address t AVQV Port 0 Data Out New Data Out Data: P0.0 - P0.7 = D0 - D7 Addresses: P1.0 - P1.7 = A0 - A7 P2.0 - P2.
C515C ROM/OTP Verification Mode 2 Parameter Symbol Limit Values Unit min. typ. max. – CLP – ns – 6 CLP – ns – – 2 CLP ns 4 CLP – – ns P3.5 setup to ALE low tAWD tACY tDVA tDSA tAS – tCL – ns Oscillator frequency 1 / CLP 4 – 6 MHz ALE pulse width ALE period Data valid after ALE Data stable after ALE t ACY t AWD ALE t DSA t DVA Port 0 Data Valid t AS P3.
C515C VDD - 0.5 V 0.2 VDD + 0.9 Test Points 0.2 VDD - 0.1 0.45 V MCT00039 AC Inputs during testing are driven at VDD - 0.5 V for a logic ‘1’ and 0.45 V for a logic ‘0’. Timing measurements are made at VIHmin for a logic ‘1’ and VILmax for a logic ‘0’. Figure 41 AC Testing: Input, Output Waveforms VOH -0.1 V VLoad +0.1 V Timing Reference Points VLoad VLoad -0.1 V VOL +0.
C515C Package Outlines 0.65 0.3 ±0.08 H 7˚max 0.15 +0.08 -0.02 0.25 min 2 +0.1 -0.05 2.45 max P-MQFP-80-1 (Plastic Metric Quad Flat Package) 0.88 C 0.1 12.35 0.12 17.2 0.2 A-B D 80x 0.2 A-B D H 4x 14 1) M A-B D C 80x D B 14 1) 17.2 A 80 1 Index Marking 0.6x45˚ 1) Does not include plastic or metal protrusions of 0.25 max per side GPM05249 You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”: http://www.infineon.com/products.
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