Datasheet

C515C
Data Sheet 15 2003-02
CPU
The C515C is efficient both as a controller and as an arithmetic processor. It has
extensive facilities for binary and BCD arithmetic and excels in its bit-handling
capabilities. Efficient use of program memory results from an instruction set consisting
of 44% one-byte, 41% two-byte, and 15% three-byte instructions. With a 6 MHz crystal,
58% of the instructions are executed in 1
µs (10 MHz: 600 ns).
PSW
Special Function Register (D0
H
) Reset Value: 00
H
Bit Function
CY Carry Flag
Used by arithmetic instruction.
AC Auxiliary Carry Flag
Used by instructions which execute BCD operations.
F0 General Purpose Flag
RS1
RS0
Register Bank select control bits
These bits are used to select one of the four register banks.
OV Overflow Flag
Used by arithmetic instruction.
F1 General Purpose Flag
PParity Flag
Set/cleared by hardware after each instruction to indicate an
odd/even number of “one” bits in the accumulator, i.e. even parity.
CY AC F0 RS1 RS0 OV F1 PD0
H
PSW
D7
H
D6
H
D5
H
D4
H
D3
H
D2
H
D1
H
D0
H
Bit No. MSB LSB
RS1 RS0 Function
0 0 Bank 0 selected, data address 00
H
-07
H
0 1 Bank 1 selected, data address 08
H
-0F
H
1 0 Bank 2 selected, data address 10
H
-17
H
1 1 Bank 3 selected, data address 18
H
-1F
H