Datasheet

C515C
Data Sheet 20 2003-02
Reset and System Clock
The reset input is an active low input at pin RESET
. Since the reset is synchronized
internally, the RESET
pin must be held low for at least two machine cycles (12 oscillator
periods) while the oscillator is running. A pullup resistor is internally connected to
V
DD
to
allow a power-up reset with an external capacitor only. An automatic reset can be
obtained when
V
DD
is applied by connecting the RESET pin to V
SS
via a capacitor.
Figure 6 shows the possible reset circuitries.
Figure 6 Reset Circuitries
Figure 7 shows the recommended oscillator circiutries for crystal and external clock
operation.
MCS02721
RESET
C515C
b)a)
c)
+
+
&
RESET
RESET
C515C
C515C