Datasheet

C515C
Data Sheet 42 2003-02
CAN Controller
The on-chip CAN controller is the functional heart which provides all resources that are
required to run the standard CAN protocol (11-bit identifiers) as well as the extended
CAN protocol (29-bit identifiers). It provides a sophisticated object layer to relieve the
CPU of as much overhead as possible when controlling many different message objects
(up to 15). This includes bus arbitration, resending of garbled messages, error handling,
interrupt generation, etc. In order to implement the physical layer, external components
have to be connected to the C515C.
The internal bus interface connects the on-chip CAN controller to the internal bus of the
microcontroller. The registers and data locations of the CAN interface are mapped to a
specific 256 bytes wide address range of the external data memory area (F700
H
to
F7FF
H
) and can be accessed using MOVX instructions. Figure 17 shows a block
diagram of the on-chip CAN controller.