Datasheet

C515C
Data Sheet 43 2003-02
Figure 17 CAN Controller Block Diagram
The TX/RX Shift Register holds the destuffed bit stream from the bus line to allow the
parallel access to the whole data or remote frame for the acceptance match test and the
parallel transfer of the frame to and from the Intelligent Memory.
The Bit Stream Processor (BSP) is a sequencer controlling the sequential data stream
between the TX/RX Shift Register, the CRC Register, and the bus line. The BSP also
controls the EML and the parallel data stream between the TX/RX Shift Register and the
Intelligent Memory such that the processes of reception, arbitration, transmission, and
error signalling are performed according to the CAN protocol. Note that the automatic
retransmission of messages which have been corrupted by noise or other external error
conditions on the bus line is handled by the BSP.
MCB02736
Bit
Timing
Logic
Timing
Generator
BTL-Configuration
CRC
Gen./Check
TX/RX Shift Register
TXDC RXDC
Intelligent
Interrupt
Register
Memory
Processor
Register
Status
Stream
Bit
Error
Logic
Management
Messages
Handlers
Control
Status +
to internal Bus
Clocks
Control
Messages
(to all)