Datasheet

C515C
Data Sheet 68 2003-02
1)
Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the V
OL
of ALE
and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these
pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF), the noise
pulse on ALE line may exceed 0.8 V. In such cases it may be desirable to qualify ALE with a Schmitt-trigger,
or use an address latch with a Schmitt-trigger strobe input.
2)
Capacitive loading on ports 0 and 2 may cause the V
OH
on ALE and PSEN to momentarily fall below the
0.9
V
DD
specification when the address lines are stabilizing.
3)
Overload conditions under operating conditions occur if the voltage on the respective pin exceeds the specified
operating range (i.e.
V
OV
> V
DD
+ 0.5 V or V
OV
< V
SS
- 0.5 V). The absolute sum of input overload currents on
all port pins may not exceed 50 mA. The supply voltage (
V
DD
and V
SS
) must remain within the specified limits.
4)
Not 100% tested, guaranteed by design characterization.