Datasheet

C515C
Data Sheet 78 2003-02
Note: The 10 MHz values in the tables are given as an example for a typical duty cycle
variation of the oscillator clock from 0.4 to 0.6.
SSC Interface Characteristics
Parameter Symbol Limit Values Unit
min. max.
Clock Cycle Time:
Master Mode
Slave Mode
t
SCLK
t
SCLK
0.4
1.0
–
–
µs
µs
Clock high time
t
SCH
360 – ns
Clock low time
t
SCL
360 – ns
Data output delay
t
D
– 100 ns
Data output hold
t
HO
0–ns
Data input setup
t
S
100 – ns
Data input hold
t
HI
100 – ns
TC bit set delay
t
DTC
–8 CLPns
External Clock Drive at XTAL2
Parameter Symbol CPU Clock = 10 MHz
Duty cycle 0.4 to 0.6
Variable CPU Clock
1/CLP = 2 to 10 MHz
Unit
min. max. min. max.
Oscillator period CLP 100 100 100 500 ns
High time TCL
H
40 – 40 CLP - TCL
L
ns
Low time TCL
L
40 – 40 CLP - TCL
H
ns
Rise time
t
R
–12– 12 ns
Fall time
t
F
–12– 12 ns
Oscillator duty
cycle
DC 0.4 0.6 40 / CLP 1 - 40 / CLP –
Clock cycle TCL 40 60 CLP
× DC
min
CLP × DC
max
ns