Datasheet

C515C

Data Sheet 82 2003-02

Figure 34 SSC Timing

Notes:

1. Shown is the data/clock relationship for CPOL = CPHA = 1. The timing diagram is

valid for the other cases accordingly.

2. In the case of slave mode and CPHA = 0, the output delay for the MSB applies to the

falling edge of SLS

(if transmitter is enabled).

3. In the case of master mode and CPHA = 0, the MSB becomes valid after the data

has been written into the shift register, i.e. at least one half SCLK clock cycle before

the first clock transition.

MCT02417

SCLK

STO

SRI

SCL

MSB LSB

SCH

SCLK

DTC