Datasheet

XC164-32
Derivatives
Functional Description
Data Sheet 21 V1.1, 2006-08
3.3 Central Processing Unit (CPU)
The main core of the CPU consists of a 5-stage execution pipeline with a 2-stage
instruction-fetch pipeline, a 16-bit arithmetic and logic unit (ALU), a 32-bit/40-bit multiply
and accumulate unit (MAC), a register-file providing three register banks, and dedicated
SFRs. The ALU features a multiply and divide unit, a bit-mask generator, and a barrel
shifter.
Figure 4 CPU Block Diagram
Based on these hardware provisions, most of the XC164CS’s instructions can be
executed in just one machine cycle which requires 25 ns at 40 MHz CPU clock. For
DPRAM
CPU
IPIP
RF
R0
R1
GPRs
R14
R15
R0
R1
GPRs
R14
R15
IFU
Injection/
Exception
Handler
ADU
MAC
mca04917_x.vsd
CPUCON1
CPUCON2
CSP IP
Return
Stack
FIFO
Branch
Unit
Prefetch
Unit
VECSEG
TFR
+/-
IDX0
IDX1
QX0
QX1
QR0
QR1
DPP0
DPP1
DPP2
DPP3
SPSEG
SP
STKOV
STKUN
+/-
MRW
MCW
MSW
MAL
+/-
MAH
Multiply
Unit
ALU
Division Unit
M ultiply Unit
Bit-Mask-Gen.
Barrel-Shifter
+/-
MDC
PSW
MDH
ZEROS
MDL
ONES
R0
R1
GPRs
R14
R15
CP
WB
Buffer
2-Stage
Prefetch
Pipeline
5-Stage
Pipeline
R0
R1
GPRs
R14
R15
PMU
DMU
DSRAM
EBC
Peripherals
PSRAM
Flash/ROM