Data Sheet, V3.3, Feb. 2005 C167CR C167SR 16-Bit Single-Chip Microcontroller Microcontrollers N e v e r s t o p t h i n k i n g .
Edition 2005-02 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 München, Germany © Infineon Technologies AG 2005. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved.
Data Sheet, V3.3, Feb. 2005 C167CR C167SR 16-Bit Single-Chip Microcontroller Microcontrollers N e v e r s t o p t h i n k i n g .
C167CR, C167SR Revision History: 2005-02 V3.3 Previous Version: V3.2, 2001-07 V3.1, 2000-04 V3.0, 2000-02 1999-10 (Introduction of clock-related timing) 1999-06 1999-03 (Summarizes and replaces all older docs) 1998-03 (C167SR/CR, 25 MHz Addendum) 07.97 / 12.96 (C167CR-4RM) 12.96 (C167CR-16RM) 06.95 (C167CR, C167SR) 06.94 / 05.
C167CR C167SR Table of Contents Table of Contents Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 2.1 2.2 2.3 General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16-Bit Single-Chip Microcontroller C166 Family 1 • • • • • • • • • C167CR/C167SR Summary of Features High Performance 16-bit CPU with 4-Stage Pipeline – 80/60 ns Instruction Cycle Time at 25/33 MHz CPU Clock – 400/303 ns Multiplication (16 × 16 bits), 800/606 ns Division (32 / 16 bits) – Enhanced Boolean Bit Manipulation Facilities – Additional Instructions to Support HLL and Operating Systems – Register-Based Design with Multiple Variable Register Banks – Single-Cycle Context Switching Support – 16
C167CR C167SR Summary of Features • • • • • Up to 111 General Purpose I/O Lines, partly with Selectable Input Thresholds and Hysteresis Supported by a Large Range of Development Tools like C-Compilers, Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers, Programming Boards On-Chip Bootstrap Loader 144-Pin MQFP Package 176-Pin BGA Package1) Ordering Information The ordering code for Infineon microcontrollers provides an exact reference to the req
C167CR C167SR Summary of Features Table 1 C167CR Derivative Synopsis Derivative1) Program ROM Size XRAM Size Operating Frequency Package SAK-C167SR-LM SAB-C167SR-LM – 2 Kbytes 25 MHz P-MQFP-144-8 SAK-C167SR-L33M SAB-C167SR-L33M – 2 Kbytes 33 MHz P-MQFP-144-8 SAK-C167CR-LM SAF-C167CR-LM SAB-C167CR-LM – 2 Kbytes 25 MHz P-MQFP-144-8 SAK-C167CR-L33M SAB-C167CR-L33M – 2 Kbytes 33 MHz P-MQFP-144-8 SAK-C167CR-4RM SAB-C167CR-4RM 32 Kbytes 2 Kbytes 25 MHz P-MQFP-144-8 SAK-C167CR-4R33M
C167CR C167SR General Device Information 2 General Device Information 2.1 Introduction The C167CR derivatives are high performance derivatives of the Infineon C166 Family of full featured single-chip CMOS microcontrollers. They combine high CPU performance (up to 16.5 million instructions per second) with high peripheral functionality and enhanced IO-capabilities. They also provide clock generation via PLL and various on-chip memory modules such as program ROM, internal RAM, and extension RAM.
C167CR C167SR General Device Information 2.2 Pin Configuration and Definition for P-MQFP-144-8 The pins of the C167CR are described in detail in Table 2, including all their alternate functions. Figure 2 summarizes all pins in a condensed way, showing their location on the 4 sides of the package. P6.0/CS0 P6.1/CS1 P6.2/CS2 P6.3/CS3 P6.4/CS4 P6.5/HOLD P6.6/HLDA P6.7/BREQ P8.0/CC16IO P8.1/CC17IO P8.2/CC18IO P8.3/CC19IO P8.4/CC20IO P8.5/CC21IO P8.6/CC22IO P8.
C167CR C167SR General Device Information Table 2 Pin Definitions and Functions P-MQFP-144-8 Symbol Pin No. Input Function Outp. P6 IO P6.0 P6.1 P6.2 P6.3 P6.4 P6.5 P6.6 1 2 3 4 5 6 7 O O O O O I I/O P6.7 8 O IO P8 P8.0 P8.1 P8.2 P8.3 P8.4 P8.5 P8.6 P8.7 9 10 11 12 13 14 15 16 Data Sheet I/O I/O I/O I/O I/O I/O I/O I/O Port 6 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits.
C167CR C167SR General Device Information Table 2 Pin Definitions and Functions P-MQFP-144-8 (cont’d) Symbol Pin No. Input Function Outp. P7 IO P7.0 P7.1 P7.2 P7.3 P7.4 P7.5 P7.6 P7.7 19 20 21 22 23 24 25 26 I P5 P5.0 P5.1 P5.2 P5.3 P5.4 P5.5 P5.6 P5.7 P5.8 P5.9 P5.10 P5.11 P5.12 P5.13 P5.14 P5.15 O O O O I/O I/O I/O I/O 27 28 29 30 31 32 33 34 35 36 39 40 41 42 43 44 Data Sheet I I I I I I I I I I I I I I I I Port 7 is an 8-bit bidirectional I/O port.
C167CR C167SR General Device Information Table 2 Pin Definitions and Functions P-MQFP-144-8 (cont’d) Symbol Pin No. Input Function Outp. P2 IO P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P2.8 47 48 49 50 51 52 53 54 57 P2.9 58 P2.10 59 P2.11 60 P2.12 61 P2.13 62 P2.14 63 P2.15 64 Data Sheet I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O I I/O I I/O I I/O I I/O I I/O I I/O I I Port 2 is a 16-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits.
C167CR C167SR General Device Information Table 2 Pin Definitions and Functions P-MQFP-144-8 (cont’d) Symbol Pin No. Input Function Outp. P3 IO P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P3.8 P3.9 P3.10 P3.11 P3.12 65 66 67 68 69 70 73 74 75 76 77 78 79 P3.13 P3.15 80 81 I O I O I I I I I/O I/O O I/O O O I/O O OWE (VPP) 84 I Data Sheet Port 3 is a 15-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits.
C167CR C167SR General Device Information Table 2 Pin Definitions and Functions P-MQFP-144-8 (cont’d) Symbol Pin No. Input Function Outp. P4 IO Port 4 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state.
C167CR C167SR General Device Information Table 2 Pin Definitions and Functions P-MQFP-144-8 (cont’d) Symbol Pin No. Input Function Outp. PORT0 P0L.0-7 100107 P0H.0-7 108, 111117 IO PORT0 consists of the two 8-bit bidirectional I/O ports P0L and P0H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state.
C167CR C167SR General Device Information Table 2 Pin Definitions and Functions P-MQFP-144-8 (cont’d) Symbol Pin No. Input Function Outp. RSTIN I/O 140 Reset Input with Schmitt-Trigger characteristics. A low level at this pin while the oscillator is running resets the C167CR. An internal pull-up resistor permits power-on reset using only a capacitor connected to VSS. A spike filter suppresses input pulses < 10 ns. Input pulses > 100 ns safely pass the filter.
C167CR C167SR General Device Information Table 2 Pin Definitions and Functions P-MQFP-144-8 (cont’d) Symbol Pin No. Input Function Outp. VDD 17, 46, – 56, 72, 82, 93, 109, 126, 136, 144 Digital Supply Voltage: + 5 V during normal operation and idle mode. ≥ 2.5 V during power down mode. VSS 18, 45, – 55, 71, 83, 94, 110, 127, 139, 143 Digital Ground.
C167CR C167SR General Device Information 2.3 Pin Configuration and Definition for P-BGA-176-2 The pins1) of the C167CR are described in detail in Table 3, including all their alternate functions. Figure 3 summarizes all pins in a condensed way, showing their location on the bottom of the package. Note: The P-MQFP-144-8 is described in Table 2 and Figure 2. 1 2 A 3 4 5 6 7 8 9 10 11 12 13 14 P 5 .5 P 5.2 P 5.0 P 7 .7 P 7.3 V SS P 8 .5 P 8.1 P 6.7 P 6 .4 P 6.0 P 7 .6 P 7.
C167CR C167SR General Device Information Table 3 Pin Definitions and Functions P-BGA-176-2 Symbol Pin Num. Input Function Outp. P5 I P5.0 P5.1 P5.2 P5.3 P5.4 P5.5 P5.6 P5.7 P5.8 P5.9 P5.10 P5.11 P5.12 P5.13 P5.14 P5.15 A5 D5 A4 C5 B4 A3 C4 D4 B3 C3 D3 C1 D1 D2 E3 E2 IO P7 P7.0 P7.1 P7.2 P7.3 P7.4 P7.5 P7.6 P7.7 I I I I I I I I I I I I I I I I D7 C7 B7 A7 D6 C6 B6 A6 Data Sheet O O O O I/O I/O I/O I/O Port 5 is a 16-bit input-only port with Schmitt-Trigger characteristic.
C167CR C167SR General Device Information Table 3 Pin Definitions and Functions P-BGA-176-2 (cont’d) Symbol Pin Num. Input Function Outp. P8 IO P8.0 P8.1 P8.2 P8.3 P8.4 P8.5 P8.6 P8.7 B10 A10 D9 C9 B9 A9 D8 C8 I/O I/O I/O I/O I/O I/O I/O I/O IO P6 P6.0 P6.1 P6.2 P6.3 P6.4 P6.5 P6.6 A13 B12 D10 C11 A12 B11 C10 O O O O O I I/O P6.7 A11 O NMI C14 I Data Sheet Port 8 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits.
C167CR C167SR General Device Information Table 3 Pin Definitions and Functions P-BGA-176-2 (cont’d) Symbol Pin Num. Input Function Outp. XTAL2 XTAL1 D13 C13 O I XTAL2: XTAL1: RST OUT D12 O Internal Reset Indication Output. This pin is set to a low level when the part is executing either a hardware-, a software- or a watchdog timer reset. RSTOUT remains low until the EINIT (end of initialization) instruction is executed. RSTIN E11 I/O Reset Input with Schmitt-Trigger characteristics.
C167CR C167SR General Device Information Table 3 Pin Definitions and Functions P-BGA-176-2 (cont’d) Symbol Pin Num. Input Function Outp. PORT1 P1L.0-7 K13, K14, J13, J14, H11, H12, H13, G11 P1H.0-3 G13, F11, F12, G14 F13 P1H.4 F14 P1H.5 E14 P1H.6 E13 P1H.7 IO PORT0 P0L.0-7 N10, L9, P11, M10, N11, M11, P12, N12 P0H.0-7 L10, K11, L12, L14, L13, K12, J11, J12 IO PORT0 consists of the two 8-bit bidirectional I/O ports P0L and P0H. It is bit-wise programmable for input or output via direction bits.
C167CR C167SR General Device Information Table 3 Pin Definitions and Functions P-BGA-176-2 (cont’d) Symbol Pin Num. Input Function Outp. EA M9 I External Access Enable pin. A low level at this pin during and after Reset forces the C167CR to begin instruction execution out of external memory. A high level forces execution out of the internal program memory. “ROMless” versions must have this pin tied to ‘0’. WR/ WRL N9 O External Memory Write Strobe.
C167CR C167SR General Device Information Table 3 Pin Definitions and Functions P-BGA-176-2 (cont’d) Symbol Pin Num. Input Function Outp. OWE (VPP) I Oscillator Watchdog Enable. This input enables the oscillator watchdog when high or disables it when low e.g. for testing purposes. An internal pull-up device holds this input high if nothing is driving it. For normal operation pin OWE should be high or not connected. In order to drive pin OWE low draw a current of at least 200 µA.
C167CR C167SR General Device Information Table 3 Pin Definitions and Functions P-BGA-176-2 (cont’d) Symbol Pin Num. Input Function Outp. P2 IO I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O I I/O I I/O I I/O I I/O I I/O I I/O I I Port 2 is a 16-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 2 outputs can be configured as push/pull or open drain drivers.
C167CR C167SR General Device Information Table 3 Pin Definitions and Functions P-BGA-176-2 (cont’d) Symbol Pin Num. Input Function Outp. VDD B8, C12, D14, F1, H3, H14, K4, M5, M12, P8 – Digital Supply Voltage: + 5 V during normal operation and idle mode. ≥ 2.5 V during power down mode. VSS A8, D11, E1, E12, G12, H2, L3, L5, L11, M8 – Digital Ground.
C167CR C167SR Functional Description 3 Functional Description The architecture of the C167CR combines advantages of both RISC and CISC processors and of advanced peripheral subsystems in a very well-balanced way. In addition the on-chip memory blocks allow the design of compact systems with maximum performance. The following block diagram gives an overview of the different on-chip components and of the advanced, high bandwidth internal bus structure of the C167CR.
C167CR C167SR Functional Description 3.1 Memory Organization The memory space of the C167CR is configured in a Von Neumann architecture which means that code memory, data memory, registers and I/O ports are organized within the same linear address space which includes 16 Mbytes. The entire memory space can be accessed bytewise or wordwise. Particular portions of the on-chip memory have additionally been made directly bitaddressable.
C167CR C167SR Functional Description 3.2 External Bus Controller All of the external memory accesses are performed by a particular on-chip External Bus Controller (EBC).
C167CR C167SR Functional Description Note: When the on-chip CAN Module is to be used the segment address output on Port 4 must be limited to 4 bits (i.e. A19 … A16) in order to enable the alternate function of the CAN interface pins. CS lines can be used to increase the total amount of addressable external memory. Data Sheet 29 V3.
C167CR C167SR Functional Description 3.3 Central Processing Unit (CPU) The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a separate multiply and divide unit, a bit-mask generator and a barrel shifter. Based on these hardware provisions, most of the C167CR’s instructions can be executed in just one machine cycle which requires 60 ns at 33 MHz CPU clock.
C167CR C167SR Functional Description The CPU has a register context consisting of up to 16 wordwide GPRs at its disposal. These 16 GPRs are physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the base address of the active register bank to be accessed by the CPU at any time. The number of register banks is only restricted by the available internal RAM space. For easy parameter passing, a register bank may overlap others.
C167CR C167SR Functional Description 3.4 Interrupt System With an interrupt response time within a range from just 5 to 12 CPU clocks (in case of internal program execution), the C167CR is capable of reacting very fast to the occurrence of non-deterministic events. The architecture of the C167CR supports several mechanisms for fast and flexible response to service requests that can be generated from various sources internal or external to the microcontroller.
C167CR C167SR Functional Description Table 4 C167CR Interrupt Nodes Source of Interrupt or Request PEC Service Request Flag Enable Flag Interrupt Vector Vector Location Trap Number CAPCOM Register 0 CC0IR CC0IE CC0INT 00’0040H 10H CAPCOM Register 1 CC1IR CC1IE CC1INT 00’0044H 11H CAPCOM Register 2 CC2IR CC2IE CC2INT 00’0048H 12H CAPCOM Register 3 CC3IR CC3IE CC3INT 00’004CH 13H CAPCOM Register 4 CC4IR CC4IE CC4INT 00’0050H 14H CAPCOM Register 5 CC5IR CC5IE CC5INT 00’
C167CR C167SR Functional Description Table 4 C167CR Interrupt Nodes (cont’d) Source of Interrupt or Request PEC Service Request Flag Enable Flag Interrupt Vector Vector Location Trap Number CAPCOM Register 30 CC30IR CC30IE CC30INT 00’0114H 45H CAPCOM Register 31 CC31IR CC31IE CC31INT 00’0118H 46H CAPCOM Timer 0 T0IR T0IE T0INT 00’0080H 20H CAPCOM Timer 1 T1IR T1IE T1INT 00’0084H 21H CAPCOM Timer 7 T7IR T7IE T7INT 00’00F4H 3DH CAPCOM Timer 8 T8IR T8IE T8INT 00’00F8H
C167CR C167SR Functional Description The C167CR also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware traps cause immediate non-maskable system reaction which is similar to a standard interrupt service (branching to a dedicated vector table location). The occurrence of a hardware trap is additionally signified by an individual bit in the trap flag register (TFR).
C167CR C167SR Functional Description 3.5 Capture/Compare (CAPCOM) Units The CAPCOM units support generation and control of timing sequences on up to 32 channels with a maximum resolution of 16 TCL. The CAPCOM units are typically used to handle high speed I/O tasks such as pulse and waveform generation, pulse width modulation (PMW), Digital to Analog (D/A) conversion, software timing, or time recording relative to external events.
C167CR C167SR Functional Description Table 6 Compare Modes (CAPCOM) Compare Modes Function Mode 0 Interrupt-only compare mode; several compare interrupts per timer period are possible Mode 1 Pin toggles on each compare match; several compare events per timer period are possible Mode 2 Interrupt-only compare mode; only one compare interrupt per timer period is generated Mode 3 Pin set ‘1’ on match; pin reset ‘0’ on compare time overflow; only one compare event per timer period is generated Double
C167CR C167SR Functional Description Reload Reg. TxREL fCPU 2n : 1 TxIN Tx Input Control CAPCOM Timer Tx Mode Control (Capture or Compare) 16-Bit Capture/ Compare Registers Ty Input Control CAPCOM Timer Ty Interrupt Request (TxIR) GPT2 Timer T6 Over/Underflow CCxIO 16 Capture Inputs 16 Compare Outputs 16 Capture/Compare Interrupt Request CCxIO fCPU 2n : 1 GPT2 Timer T6 Over/Underflow Interrupt Request (TyIR) Reload Reg. TyREL MCB02143B x = 0, 7 y = 1, 8 n = 3 … 10 Figure 6 3.
C167CR C167SR Functional Description 3.7 General Purpose Timer (GPT) Unit The GPT unit represents a very flexible multifunctional timer/counter structure which may be used for many different time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. The GPT unit incorporates five 16-bit timers which are organized in two separate modules, GPT1 and GPT2.
C167CR C167SR Functional Description U/D T2EUD fCPU 2n : 1 T2IN Interrupt Request GPT1 Timer T2 T2 Mode Control Reload Capture fCPU Interrupt Request n 2 :1 Toggle FF T3 Mode Control T3IN GPT1 Timer T3 T3OTL T3OUT U/D T3EUD Other Timers Capture Reload T4IN fCPU 2n : 1 T4 Mode Control GPT1 Timer T4 Interrupt Request U/D T4EUD MCT02141 n = 3 … 10 Figure 7 Block Diagram of GPT1 With its maximum resolution of 8 TCL, the GPT2 module provides precise event control and time measureme
C167CR C167SR Functional Description The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of GPT1 timer T3’s inputs T3IN and/or T3EUD. This is especially advantageous when T3 operates in Incremental Interface Mode.
C167CR C167SR Functional Description 3.8 A/D Converter For analog signal measurement, a 10-bit A/D converter with 16 multiplexed input channels and a sample and hold circuit has been integrated on-chip. It uses the method of successive approximation. The sample time (for loading the capacitors) and the conversion time is programmable and can so be adjusted to the external circuitry.
C167CR C167SR Functional Description 3.9 Serial Channels Serial communication with other microcontrollers, processors, terminals or external peripheral components is provided by two serial interfaces with different functionality, an Asynchronous/Synchronous Serial Channel (ASC0) and a High-Speed Synchronous Serial Channel (SSC). The ASC0 is upward compatible with the serial ports of the Infineon 8-bit microcontroller families and supports full-duplex asynchronous communication at up to 781 kbit/s/1.
C167CR C167SR Functional Description 3.10 CAN-Module The integrated CAN-Module handles the completely autonomous transmission and reception of CAN frames in accordance with the CAN specification V2.0 part B (active), i.e. the on-chip CAN-Module can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. The module provides Full CAN functionality on up to 15 message objects. Message object 15 may be configured for Basic CAN functionality.
C167CR C167SR Functional Description 3.12 Parallel Ports The C167CR provides up to 111 I/O lines which are organized into eight input/output ports and one input port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O ports are true bidirectional ports which are switched to high impedance state when configured as inputs.
C167CR C167SR Functional Description 3.13 Oscillator Watchdog The Oscillator Watchdog (OWD) monitors the clock signal generated by the on-chip oscillator (either with a crystal or via external clock drive). For this operation the PLL provides a clock signal which is used to supervise transitions on the oscillator clock. This PLL clock is independent from the XTAL1 clock.
C167CR C167SR Functional Description 3.14 Instruction Set Summary Table 7 lists the instructions of the C167CR in a condensed way. The various addressing modes that can be used with a specific instruction, the operation of the instructions, parameters for conditional execution of instructions, and the opcodes for each instruction can be found in the “C166 Family Instruction Set Manual”. This document also provides a detailed description of each instruction.
C167CR C167SR Functional Description Table 7 Instruction Set Summary (cont’d) Mnemonic Description Bytes PRIOR Determine number of shift cycles to normalize direct word GPR and store result in direct word GPR 2 SHL / SHR Shift left/right direct word GPR 2 ROL / ROR Rotate left/right direct word GPR 2 ASHR Arithmetic (sign bit) shift right direct word GPR 2 MOV(B) Move word (byte) data 2/4 MOVBS Move byte operand to word operand with sign extension 2/4 MOVBZ Move byte operand to word
C167CR C167SR Functional Description Table 7 Instruction Set Summary (cont’d) Mnemonic Description Bytes DISWDT Disable Watchdog Timer 4 EINIT Signify End-of-Initialization on RSTOUT-pin 4 ATOMIC Begin ATOMIC sequence 2 EXTR Begin EXTended Register sequence 2 EXTP(R) Begin EXTended Page (and Register) sequence 2/4 EXTS(R) Begin EXTended Segment (and Register) sequence 2/4 NOP Null operation 2 Data Sheet 49 V3.
C167CR C167SR Functional Description 3.15 Special Function Registers Overview The following table lists all SFRs which are implemented in the C167CR in alphabetical order. Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the Extended SFR-Space (ESFRs) are marked with the letter “E” in column “Physical Address”. Registers within on-chip X-peripherals are marked with the letter “X” in column “Physical Address”. An SFR can be specified via its individual mnemonic name.
C167CR C167SR Functional Description Table 8 C167CR Registers, Ordered by Name (cont’d) Name Physical Address C1IR EF02H C1LGML EF0AH X – CAN1 Lower Global Mask Long UUUUH C1LMLM EF0EH X – CAN1 Lower Mask of Last Message UUUUH C1UAR EFn2H X – CAN1 Upper Arbitration Register (message n) UUUUH C1UGML EF08H X – CAN1 Upper Global Mask Long UUUUH C1UMLM EF0CH X – CAN1 Upper Mask of Last Message UUUUH CAPREL FE4AH 25H GPT2 Capture/Reload Register 0000H CC0 FE80H 40H CAPCOM Regi
C167CR C167SR Functional Description Table 8 Name C167CR Registers, Ordered by Name (cont’d) Physical Address 8-Bit Description Addr. CC19IC b F166H E B3H CC1IC b FF7AH CC2 CC20 CC20IC CC21 CC21IC CC22 CC22IC CC23 Reset Value CAPCOM Reg. 19 Interrupt Ctrl. Reg. 0000H BDH CAPCOM Reg. 1 Interrupt Ctrl. Reg. 0000H FE84H 42H CAPCOM Register 2 0000H FE68H 34H CAPCOM Register 20 0000H b F168H E B4H CAPCOM Reg. 20 Interrupt Ctrl. Reg.
C167CR C167SR Functional Description Table 8 C167CR Registers, Ordered by Name (cont’d) Name Physical Address 8-Bit Description Addr. Reset Value CC4 FE88H 44H CAPCOM Register 4 0000H b FF80H C0H CAPCOM Reg. 4 Interrupt Ctrl. Reg. 0000H FE8AH 45H CAPCOM Register 5 0000H b FF82H C1H CAPCOM Register 5 Interrupt Ctrl. Reg. 0000H FE8CH 46H CAPCOM Register 6 0000H b FF84H C2H CAPCOM Reg. 6 Interrupt Ctrl. Reg. 0000H FE8EH 47H CAPCOM Register 7 0000H b FF86H C3H CAPCOM Reg.
C167CR C167SR Functional Description Table 8 Name C167CR Registers, Ordered by Name (cont’d) Physical Address 8-Bit Description Addr. Reset Value DP4 b FFCAH E5H Port 4 Direction Control Register 00H DP6 b FFCEH E7H Port 6 Direction Control Register 00H DP7 b FFD2H E9H Port 7 Direction Control Register 00H DP8 b FFD6H EBH Port 8 Direction Control Register 00H DPP0 FE00H 00H CPU Data Page Pointer 0 Reg. (10 bits) 0000H DPP1 FE02H 01H CPU Data Page Pointer 1 Reg.
C167CR C167SR Functional Description Table 8 C167CR Registers, Ordered by Name (cont’d) Name Physical Address 8-Bit Description Addr.
C167CR C167SR Functional Description Table 8 Name C167CR Registers, Ordered by Name (cont’d) 8-Bit Description Addr. Reset Value b FF70H B8H Serial Chan. 0 Error Interrupt Ctrl. Reg. 0000H FEB2H 59H Serial Channel 0 Receive Buffer Reg.
C167CR C167SR Functional Description Table 8 Name C167CR Registers, Ordered by Name (cont’d) 8-Bit Description Addr.
C167CR C167SR Electrical Parameters 4 Electrical Parameters 4.1 General Parameters Table 9 Absolute Maximum Rating Parameters Parameter Symbol Limit Values Unit Notes Min. Max. TST TJ VDD -65 150 °C – -40 150 °C under bias -0.5 6.5 V – Voltage on any pin with respect to ground (VSS) VIN -0.5 VDD + 0.
C167CR C167SR Electrical Parameters Operating Conditions The following operating conditions must not be exceeded in order to ensure correct operation of the C167CR. All parameters specified in the following sections refer to these operating conditions, unless otherwise noticed.
C167CR C167SR Electrical Parameters Parameter Interpretation The parameters listed in the following partly represent the characteristics of the C167CR and partly its demands on the system. To aid in interpreting the parameters right, when evaluating them for a design, they are marked in column “Symbol”: CC (Controller Characteristics): The logic of the C167CR will provide signals with the respective timing characteristics.
C167CR C167SR Electrical Parameters Table 11 DC Characteristics (Operating Conditions apply)1) (cont’d) Parameter Symbol Limit Values Min. Unit Test Condition Max. Output high voltage3) (PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT, RSTOUT) VOH CC 2.4 Output high voltage3) (all other outputs) VOH1 CC 2.
C167CR C167SR Electrical Parameters 9) This specification is valid during Reset and during Adapt-mode. 10) Not subject to production test - verified by design/characterization. Table 12 Power Consumption C167CR (Operating Conditions apply) Parameter Symbol Limit Values Min. Max. Unit Test Condition Power supply current (active) with all peripherals active IDD – 15 + 2.5 × fCPU mA Idle mode supply current IID – 10 + 1.
C167CR C167SR Electrical Parameters I [mA] 140 IDDmax 120 IDDtyp 100 80 60 IIDmax IIDtyp 40 20 10 Figure 9 Data Sheet 20 30 40 fCPU [MHz] Supply/Idle Current as a Function of Operating Frequency 63 V3.
C167CR C167SR Electrical Parameters 4.3 Table 13 Analog/Digital Converter Parameters A/D Converter Characteristics (Operating Conditions apply) Parameter Symbol VAREF SR Analog reference ground VAGND SR Analog input voltage range VAIN SR Basic clock frequency fBC Conversion time tC CC Analog reference supply Limit Values Unit Test Condition Min. Max. 4.0 1) VSS - 0.1 VAGND VDD + 0.1 V VSS + 0.2 V VAREF V 0.5 6.
C167CR C167SR Electrical Parameters 8) During the sample time the input capacitance CAIN can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result. Values for the sample time tS depend on programming and can be taken from Table 14.
C167CR C167SR Electrical Parameters 4.4 AC Parameters 4.4.1 Definition of Internal Timing The internal operation of the C167CR is controlled by the internal CPU clock fCPU. Both edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles) operations. The specification of the external timing (AC Characteristics) therefore depends on the time between two consecutive edges of the CPU clock, called “TCL” (see Figure 10).
C167CR C167SR Electrical Parameters upper half of PORT0 (P0H), i.e. bitfield CLKCFG represents the logic levels on pins P0.15-13 (P0H.7-5). Table 15 associates the combinations of these three bits with the respective clock generation mode. Table 15 C167CR Clock Generation Modes CLKCFG (P0H.7-5) CPU Frequency External Clock fCPU = fOSC × F Input Range1) Notes 111 fOSC × 4 fOSC × 3 fOSC × 2 fOSC × 5 fOSC × 1 fOSC × 1.5 fOSC / 2 fOSC × 2.5 2.5 to 8.25 MHz Default configuration 3.
C167CR C167SR Electrical Parameters The timings listed in the AC Characteristics that refer to TCLs therefore must be calculated using the minimum TCL that is possible under the respective circumstances. The actual minimum value for TCL depends on the jitter of the PLL.
C167CR C167SR Electrical Parameters Direct Drive When direct drive is configured (CLKCFG = 011B) the on-chip phase locked loop is disabled and the CPU clock is directly driven from the internal oscillator with the input clock signal. The frequency of fCPU directly follows the frequency of fOSC so the high and low time of fCPU (i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock fOSC.
C167CR C167SR Electrical Parameters 4.4.2 Table 16 External Clock Drive XTAL1 External Clock Drive Characteristics (Operating Conditions apply) Parameter Symbol Oscillator period High time2) Low time2) Rise time2) Fall time2) tOSC t1 t2 t3 t4 Direct Drive 1:1 Prescaler 2:1 PLL 1:N Unit Min. Max. Min. Max. Min. Max.
C167CR C167SR Electrical Parameters 4.4.3 Testing Waveforms 2.4 V 1.8 V 1.8 V Test Points 0.8 V 0.45 V 0.8 V AC inputs during testing are driven at 2.4 V for a logic ’1’ and 0.45 V for a logic ’0’. Timing measurements are made at VIH min for a logic ’1’ and VIL max for a logic ’0’. MCA04414 Figure 13 Input Output Waveforms VLoad + 0.1 V VOH - 0.1 V Timing Reference Points VLoad - 0.1 V VOL + 0.
C167CR C167SR Electrical Parameters 4.4.4 Table 17 External Bus Timing CLKOUT Reference Signal Parameter Symbol Limits Min. tc5 tc6 tc7 tc8 tc9 CLKOUT cycle time CLKOUT high time CLKOUT low time CLKOUT rise time CLKOUT fall time CC Unit Max. 301) ns CC 8 – ns CC 6 – ns CC – 4 ns CC – 4 ns 1) The CLKOUT cycle time is influenced by the PLL jitter. For a single CLKOUT cycle (2 TCL) the deviation caused by the PLL jitter is below 1 ns (for fCPU > 25 MHz).
C167CR C167SR Electrical Parameters Table 19 External Bus Cycle Timing (Operating Conditions apply) Parameter Symbol Limits Min. Unit Max.
C167CR C167SR Electrical Parameters General Notes for the Following Timing Figures These standard notes apply to all subsequent timing figures. Additional individual notes are placed at the respective figure. 1. The falling edge of signals RD and WR/WRH/WRL/WrCS is controlled by the Read/Write delay feature (bit BUSCON.RWDCx). 2. A bus cycle is extended here, if MCTC waitstates are selected or if the READY input is sampled inactive. 3. A bus cycle is extended here, if an MTTC waitstate is selected.
C167CR C167SR Electrical Parameters CLKOUT Normal ALE Cycle tc 11 tc10 Normal ALE Extended ALE Cycle tc 10 tc 10 Extended ALE tc 11 tc 11 tc 11 CSxL tc 10 tc 10 tc17 A23-A0 BHE, CSxE Valid tc 13 tc 12 WRL, WRH, WR, WrCS tc 19 1) tc10 tc21 tc18 D15-D0 tc20 Data OUT 2) MCTC 3) MTTC MCT04416 Figure 16 Data Sheet Demultiplexed Bus, Write Access 75 V3.
C167CR C167SR Electrical Parameters CLKOUT Normal ALE Cycle tc 11 tc 10 Normal ALE Extended ALE Cycle tc 10 tc 10 Extended ALE tc 11 tc 11 tc 11 CSxL tc10 tc10 tc17 A23-A0, BHE, CSxE Valid tc13 tc12 RD, RdCS tc13 1) tc15 tc14 D15-D0 Data IN 2) MCTC 3) MTTC MCT04417 Figure 17 Data Sheet Demultiplexed Bus, Read Access 76 V3.
C167CR C167SR Electrical Parameters CLKOUT Normal ALE Cycle tc11 tc10 Normal ALE Extended ALE Cycle tc 10 tc 10 Extended ALE tc 11 tc 11 CSxL tc 10 tc 10 tc 17 A23-A16 BHE, CSxE Valid tc 13 tc 12 WRL, WRH, WR, WrCS 1) tc 10 tc 21 AD15-AD0 (Normal ALE) tc 17 tc 10 tc 18 Low Address tc 10 tc 21 AD15-AD0 (Extended ALE) tc 19 tc 17 tc 20 Data OUT tc 10 tc 18 tc 20 Data OUT Low Address 2) MCTC 3) MTTC MCT04418 Figure 18 Data Sheet Multiplexed Bus, Write Access 77 V3.
C167CR C167SR Electrical Parameters CLKOUT Normal ALE Cycle tc 11 tc 10 Normal ALE Extended ALE Cycle tc 10 tc 10 Extended ALE tc 11 tc 11 CSxL tc 10 tc 10 tc 17 A23-A16 BHE, CSxE Valid tc 13 tc 12 RD, RdCS tc 13 1) tc 10 tc 20 tc 21 AD15-AD0 (Normal ALE) tc 17 tc 14 Low Address tc 10 Data IN tc 20 tc 21 AD15-AD0 (Extended ALE) tc 15 tc 15 tc 17 tc 14 Data IN Low Address 2) MCTC 3) MTTC MCT04419 Figure 19 Data Sheet Multiplexed Bus, Read Access 78 V3.
C167CR C167SR Electrical Parameters Bus Cycle Control via READY Input The duration of an external bus cycle can be controlled by the external circuitry via the READY input signal. Synchronous READY permits the shortest possible bus cycle but requires the input signal to be synchronous to the reference signal CLKOUT. Asynchronous READY puts no timing constraints on the input signal but incurs one waitstate minimum due to the additional synchronization stage.
C167CR C167SR Electrical Parameters Running Cycle 4) READY WS MUX/MTTC 7) CLKOUT tc 15 tc 14 Data IN tc 10 tc 18 tc 21 D15-D0 tc 20 The next external bus cycle may start here. D15-D0 Data OUT tc 13 tc 12 Command (RD, WR) tc 13 / tc 19 1) 6) tc 26 tc 25 Synchronous READY tc 26 Asynchronous READY tc 25 5) tc 25 5) tc 26 5) tc 27 tc 26 tc 25 5) 8) MCT04420 Figure 20 Data Sheet READY Timings 80 V3.
C167CR C167SR Electrical Parameters External Bus Arbitration Table 21 Bus Arbitration Timing (Operating Conditions apply) Parameter Symbol Limits Min. HOLD input setup time to CLKOUT falling edge CLKOUT to BREQ delay CLKOUT to HLDA delay CSx release1) CSx drive Other signals release1) Other signals drive1) tc28 tc29 tc30 tc31 tc32 tc33 tc34 Unit Max.
C167CR C167SR Electrical Parameters CLKOUT tc 28 HOLD tc 30 HLDA 1) tc 29 BREQ 2) tc 31 CS 3) tc 33 Other Signals MCT04421 Figure 21 External Bus Arbitration, Releasing the Bus Notes 1. The C167CR will complete the currently running bus cycle before granting bus access. 2. This is the first possibility for BREQ to get active. 3. The CS outputs will be resistive high (pull-up) after t33. Latched CS outputs are driven high for 1 TCL before the output drivers are switched off. Data Sheet 82 V3.
C167CR C167SR Electrical Parameters 5) CLKOUT tc 28 HOLD tc 30 HLDA tc 29 tc 29 BREQ tc 29 4) tc 32 CS tc 34 Other Signals MCT04422 Figure 22 External Bus Arbitration, Regaining the Bus Notes 4. This is the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated earlier, the regain-sequence is initiated by HOLD going high. Please note that HOLD may also be deactivated without the C167CR requesting the bus. 5. The next C167CR driven bus cycle may start here.
C167CR C167SR Electrical Parameters External XRAM Access If XPER-Share mode is enabled the on-chip XRAM of the C167CR can be accessed (during hold states) by an external master like an asynchronous SRAM.
C167CR C167SR Package Outlines 144x 0.12 M A-B D C 35 x 0.65 = 22.75 7˚ MAX. H 0.65 0.3 ±0.08 0.15 +0.08 -0.02 2.75 MAX. Package Outlines 0.25 MIN. 2.4 -0.1 5 0.88 ±0.15 0.1 C 31.2 0.2 A-B D 4x 28 1) 0.2 A-B D H 4x D A 31.2 28 1) B 144 1 x 45˚ 1 Index Marking 1) Does not include plastic or metal protrusion of 0.25 max.
C167CR C167SR Package Outlines 13 x 1 = 13 A1 1 13 x 1 = 13 A14 1 0.4 ±0.1 (0.56) (0.8) 2 MAX. P1 ø0.5 +0.14 -0.16 176x ø0.3 M A B C ø0.1 M C 0.2 C 1.5 ±0.5 4x 13 ±1 15 ±0.2 13 ±1 A Index Marking Index Marking (sharp edge) 15 ±0.2 B GPA09430 Figure 25 P-BGA-176-2 (Plastic Ball Grid Array Package) You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”: http://www.infineon.com/products. Data Sheet 86 Dimensions in mm V3.
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