Datasheet

C167CR
C167SR
Functional Description
Data Sheet 41 V3.3, 2005-02
The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of
GPT1 timer T3’s inputs T3IN and/or T3EUD. This is especially advantageous when T3
operates in Incremental Interface Mode.
Figure 8 Block Diagram of GPT2
MUX
2
n
: 1f
CPU
T5
Mode
Control
2
n
: 1f
CPU
T6
Mode
Control
T6OTL
T5EUD
T5IN
T3
CAPIN
T6IN
T6EUD
T6OUT
U/D
U/D
Interrupt
Request
Interrupt
Request
Interrupt
Request
Other
Timers
Clear
Capture
CT3
MCB03999
GPT2 Timer T5
GPT2 CAPREL
GPT2 Timer T6
n = 2 … 9