Datasheet

C167CR
C167SR
Electrical Parameters
Data Sheet 68 V3.3, 2005-02
The timings listed in the AC Characteristics that refer to TCLs therefore must be
calculated using the minimum TCL that is possible under the respective circumstances.
The actual minimum value for TCL depends on the jitter of the PLL. As the PLL is
constantly adjusting its output frequency so it corresponds to the applied input frequency
(crystal or oscillator) the relative deviation for periods of more than one TCL is lower than
for one single TCL (see formula and Figure 11).
For a period of N × TCL the minimum value is computed using the corresponding
deviation D
N
:
(N × TCL)
min
= N × TCL
NOM
- D
N
, D
N
[ns] = ±(13.3 + N × 6.3) / f
CPU
[MHz], (1)
where N = number of consecutive TCLs and 1 ≤ N ≤ 40.
So for a period of 3 TCLs @ 25 MHz (i.e. N = 3): D
3
= (13.3 + 3 × 6.3) / 25 = 1.288 ns,
and (3TCL)
min
= 3TCL
NOM
- 1.288 ns = 58.7 ns (@ f
CPU
= 25 MHz).
This is especially important for bus cycles using waitstates and e.g. for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter
is negligible.
Note: For all periods longer than 40 TCL the N = 40 value can be used (see Figure 11).
Figure 11 Approximated Maximum Accumulated PLL Jitter
±1
±10
1 5 10 20
D
N
±20
±26.5
ns
±30
40 and 10 MHz
This approximated formula is valid for
1 N 33 MHz.
CPU
f
25 MHz
33 MHz
40
MCD04413
N
16 MHz
20 MHz
10 MHz
Max. jitter