Datasheet

C167CR
C167SR
Electrical Parameters
Data Sheet 70 V3.3, 2005-02
4.4.2 External Clock Drive XTAL1
Figure 12 External Clock Drive XTAL1
Note: If the on-chip oscillator is used together with a crystal, the oscillator frequency is
limited to a range of 4 MHz to 40 MHz.
It is strongly recommended to measure the oscillation allowance (or margin) in the
final target system (layout) to determine the optimum parameters for the oscillator
operation. Please refer to the limits specified by the crystal supplier.
When driven by an external clock signal it will accept the specified frequency
range. Operation at lower input frequencies is possible but is guaranteed by
design only (not 100% tested).
Table 16 External Clock Drive Characteristics (Operating Conditions apply)
Parameter Symbol Direct Drive
1:1
Prescaler
2:1
PLL
1:N
Unit
Min. Max. Min. Max. Min. Max.
Oscillator period
t
OSC
SR 30 – 15 – 45
1)
1) The minimum and maximum oscillator periods for PLL operation depend on the selected CPU clock
generation mode. Please see respective table above.
500
1)
ns
High time
2)
2) The clock input signal must reach the defined levels V
IL2
and V
IH2
.
t
1
SR 15
3)
3) The minimum high and low time refers to a duty cycle of 50%. The maximum operating frequency (f
CPU
) in
direct drive mode depends on the duty cycle of the clock input signal.
–5–10–ns
Low time
2)
t
2
SR 15
3)
–5–10–ns
Rise time
2)
t
3
SR–8–5–10ns
Fall time
2)
t
4
SR–8–5–10ns
MCT02534
3
t
4
t
V
IH2
V
IL
V
DD
0.5
1
t
2
t
OSC
t