Datasheet

C167CR
C167SR
Electrical Parameters
Data Sheet 84 V3.3, 2005-02
External XRAM Access
If XPER-Share mode is enabled the on-chip XRAM of the C167CR can be accessed
(during hold states) by an external master like an asynchronous SRAM.
Figure 23 External Access to the XRAM
Table 22 XRAM Access Timing (Operating Conditions apply)
1)
1) The minimum access cycle time is 60 ns.
Parameter Symbol Limits Unit
Min. Max.
Address setup time before RD
/WR falling edge t
40
SR 4 – ns
Address hold time after RD
/WR rising edge t
41
SR 0 – ns
Data turn on delay after RD
falling edge
Read
t
42
CC 1 – ns
Data output valid delay after address latched
t
43
CC – 40 ns
Data turn off delay after RD
rising edge t
44
CC 1 14 ns
Write data setup time before WR
rising edge
Write
t
45
SR 10 – ns
Write data hold time after WR
rising edge t
46
SR 2 – ns
WR
pulse width t
47
SR 20 – ns
WR
signal recovery time t
48
SR t
40
–ns
Read Data
43
t
42
t
44
t
MCT04423
(RD, WR)
Write Data
Command
Address
40
t
45
t
47
t
46
t
48
t
41
t