Da ta She et, V2. 2, Aug . 2 00 1 C167CS-4R C167CS-L 16-Bit Single-Chip Microcontroller Microcontrollers N e v e r s t o p t h i n k i n g .
Edition 2001-08 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München, Germany © Infineon Technologies AG 2001. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved.
Da ta She et, V2. 2, Aug . 2 00 1 C167CS-4R C167CS-L 16-Bit Single-Chip Microcontroller Microcontrollers N e v e r s t o p t h i n k i n g .
C167CS Revision History: 2001-08 Previous Version: 2000-12 2000-06 1999-06 1999-03 V2.2 V2.1 (Intermediate version) V2.0 (Advance Information) Page Subjects (major changes from V2.1, 2000-12 to V2.
16-Bit Single-Chip Microcontroller C166 Family C167CS C167CS-4R, C167CS-L • High Performance 16-bit CPU with 4-Stage Pipeline – 80/60/50 ns Instruction Cycle Time at 25/33/40 MHz CPU Clock – 400/303/250 ns Multiplication (16 × 16 bit), 800/606/500 ns Division (32-/16-bit) – Enhanced Boolean Bit Manipulation Facilities – Additional Instructions to Support HLL and Operating Systems – Register-Based Design with Multiple Variable Register Banks – Single-Cycle Context Switching Support – 16 MBytes Total Linear
C167CS-4R C167CS-L • Supported by a Large Range of Development Tools like C-Compilers, Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers, Programming Boards • On-Chip Bootstrap Loader • 144-Pin MQFP Package This document describes several derivatives of the C167 group. Table 1 enumerates these derivatives and summarizes the differences. As this document refers to all of these derivatives, some descriptions may not apply to a specific product.
C167CS-4R C167CS-L Ordering Information The ordering code for Infineon microcontrollers provides an exact reference to the required product. This ordering code identifies: • the derivative itself, i.e. its function set, the temperature range, and the supply voltage • the package and the type of delivery. For the available ordering codes for the C167CS please refer to the “Product Catalog Microcontrollers”, which summarizes all available microcontroller variants.
C167CS-4R C167CS-L P6.0/CS0 P6.1/CS1 P6.2/CS2 P6.3/CS3 P6.4/CS4 P6.5/HOLD P6.6/HLDA P6.7/BREQ *P8.0/CC16IO *P8.1/CC17IO *P8.2/CC18IO *P8.3/CC19IO P8.4/CC20IO P8.5/CC21IO P8.6/CC22IO P8.7/CC23IO VDD VSS V SS V DD P1L.7/A7/AN23 P1L.6/A6/AN22 P1L.5/A5/AN21 P1L.4/A4/AN20 P1L.3/A3/AN19 P1L.2/A2/AN18 P1L.1/A1/AN17 P1L.0/A0/AN16 P0H.7/AD15 P0H.6/AD14 P0H.5/AD13 P0H.4/AD12 P0H.3/AD11 P0H.2/AD10 P0H.1/AD9 V SS V DD P1H.7/A15/CC27IO P1H.6/A14/CC26IO P1H.5/A13/CC25IO P1H.4/A12/CC24IO P1H.3/A11 P1H.2/A10 P1H.
C167CS-4R C167CS-L Table 2 Pin Definitions and Functions Symbol Pin Num. Input Outp. Function P6 IO Port 6 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 6 outputs can be configured as push/ pull or open drain drivers.
C167CS-4R C167CS-L Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Num. Input Outp. Function P7 IO Port 7 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 7 outputs can be configured as push/ pull or open drain drivers. The input threshold of Port 7 is selectable (TTL or special).
C167CS-4R C167CS-L Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Num. Input Outp. Function P2 IO Port 2 is a 16-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 2 outputs can be configured as push/ pull or open drain drivers. The input threshold of Port 2 is selectable (TTL or special).
C167CS-4R C167CS-L Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Num. Input Outp. Function P3 IO Port 3 is a 15-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 3 outputs can be configured as push/ pull or open drain drivers. The input threshold of Port 3 is selectable (TTL or special).
C167CS-4R C167CS-L Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Num. Input Outp. Function P4 IO Port 4 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. The Port 4 outputs can be configured as push/pull or open drain drivers. The input threshold of Port 4 is selectable (TTL or special).
C167CS-4R C167CS-L Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Num. Input Outp. Function ALE 98 O Address Latch Enable Output. Can be used for latching the address into external memory or an address latch in the multiplexed bus modes. EA 99 I External Access Enable pin. A low level at this pin during and after Reset forces the C167CS to begin instruction execution out of external memory. A high level forces execution out of the internal program memory.
C167CS-4R C167CS-L Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Num. Input Outp. Function PORT1 P1L.0-7 118125 P1H.0-7 128135 IO P1L.0 P1L.1 P1L.2 P1L.3 P1L.4 P1L.5 P1L.6 P1L.7 P1H.4 P1H.5 P1H.6 P1H.7 118 119 120 121 122 123 124 125 132 133 134 135 I I I I I I I I I/O I/O I/O I/O PORT1 consists of the two 8-bit bidirectional I/O ports P1L and P1H. It is bit-wise programmable for input or output via direction bits.
C167CS-4R C167CS-L Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Num. Input Outp. Function RSTIN I/O Reset Input with Schmitt-Trigger characteristics. A low level at this pin while the oscillator is running resets the C167CS. An internal pullup resistor permits power-on reset using only a capacitor connected to VSS. A spike filter suppresses input pulses <10 ns. Input pulses >100 ns safely pass the filter. The minimum duration for a safe recognition should be 100 ns + 2 CPU clock cycles.
C167CS-4R C167CS-L Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Num. Input Outp. Function VDD 17, 46, – 56, 72, 82, 93, 109, 126, 136, 144 Digital Supply Voltage: +5 V during normal operation and idle mode. ≥2.5 V during power down mode. VSS 18, 45, – 55, 71, 83, 94, 110, 127, 139, 143 Digital Ground. 1) The CAN interface lines are assigned to ports P4 and P8 under software control. Within the CAN module several assignments can be selected.
C167CS-4R C167CS-L Functional Description The architecture of the C167CS combines advantages of both RISC and CISC processors and of advanced peripheral subsystems in a very well-balanced way. In addition the on-chip memory blocks allow the design of compact systems with maximum performance. Figure 3 gives an overview of the different on-chip components and of the advanced, high bandwidth internal bus structure of the C167CS.
C167CS-4R C167CS-L Memory Organization The memory space of the C167CS is configured in a Von Neumann architecture which means that code memory, data memory, registers and I/O ports are organized within the same linear address space which includes 16 MBytes. The entire memory space can be accessed bytewise or wordwise. Particular portions of the on-chip memory have additionally been made directly bitaddressable.
C167CS-4R C167CS-L External Bus Controller All of the external memory accesses are performed by a particular on-chip External Bus Controller (EBC).
C167CS-4R C167CS-L Note: When one or both of the on-chip CAN Modules are used with the interface lines assigned to Port 4, the CAN lines override the segment address lines and the segment address output on Port 4 is therefore limited to 6/4 bits i.e. address lines A21/A19 … A16. CS lines can be used to increase the total amount of addressable external memory.
C167CS-4R C167CS-L The CPU has a register context consisting of up to 16 wordwide GPRs at its disposal. These 16 GPRs are physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the base address of the active register bank to be accessed by the CPU at any time. The number of register banks is only restricted by the available internal RAM space. For easy parameter passing, a register bank may overlap others.
C167CS-4R C167CS-L Interrupt System With an interrupt response time within a range from just 5 to 12 CPU clocks (in case of internal program execution), the C167CS is capable of reacting very fast to the occurrence of non-deterministic events. The architecture of the C167CS supports several mechanisms for fast and flexible response to service requests that can be generated from various sources internal or external to the microcontroller.
C167CS-4R C167CS-L Table 3 C167CS Interrupt Nodes Source of Interrupt or Request PEC Service Request Flag Enable Flag Interrupt Vector Vector Location Trap Number CAPCOM Register 0 CC0IR CC0IE CC0INT 00’0040H 10H CAPCOM Register 1 CC1IR CC1IE CC1INT 00’0044H 11H CAPCOM Register 2 CC2IR CC2IE CC2INT 00’0048H 12H CAPCOM Register 3 CC3IR CC3IE CC3INT 00’004CH 13H CAPCOM Register 4 CC4IR CC4IE CC4INT 00’0050H 14H CAPCOM Register 5 CC5IR CC5IE CC5INT 00’0054H 15H CAPCO
C167CS-4R C167CS-L Table 3 C167CS Interrupt Nodes (cont’d) Source of Interrupt or Request PEC Service Request Flag Enable Flag Interrupt Vector Vector Location Trap Number CAPCOM Register 30 CC30IR CC30IE CC30INT 00’0114H 45H CAPCOM Register 31 CC31IR CC31IE CC31INT 00’0118H 46H CAPCOM Timer 0 T0IR T0IE T0INT 00’0080H 20H CAPCOM Timer 1 T1IR T1IE T1INT 00’0084H 21H CAPCOM Timer 7 T7IR T7IE T7INT 00’00F4H 3DH CAPCOM Timer 8 T8IR T8IE T8INT 00’00F8H 3EH GPT1 Timer 2
C167CS-4R C167CS-L The C167CS also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware traps cause immediate non-maskable system reaction which is similar to a standard interrupt service (branching to a dedicated vector table location). The occurrence of a hardware trap is additionally signified by an individual bit in the trap flag register (TFR).
C167CS-4R C167CS-L Capture/Compare (CAPCOM) Units The CAPCOM units support generation and control of timing sequences on up to 32 channels with a maximum resolution of 16 TCL. The CAPCOM units are typically used to handle high speed I/O tasks such as pulse and waveform generation, pulse width modulation (PMW), Digital to Analog (D/A) conversion, software timing, or time recording relative to external events.
C167CS-4R C167CS-L Table 5 Compare Modes (CAPCOM) Compare Modes Function Mode 0 Interrupt-only compare mode; several compare interrupts per timer period are possible. Mode 1 Pin toggles on each compare match; several compare events per timer period are possible. Mode 2 Interrupt-only compare mode; only one compare interrupt per timer period is generated. Mode 3 Pin set ‘1’ on match; pin reset ‘0’ on compare time overflow; only one compare event per timer period is generated.
C167CS-4R C167CS-L Reload Reg. TxREL fCPU 2n : 1 TxIN Tx Input Control CAPCOM Timer Tx Mode Control (Capture or Compare) 16-Bit Capture/ Compare Registers Ty Input Control CAPCOM Timer Ty Interrupt Request (TxIR) GPT2 Timer T6 Over/Underflow CCxIO 16 Capture Inputs 16 Compare Outputs 16 Capture/Compare Interrupt Request CCxIO fCPU GPT2 Timer T6 Over/Underflow 2n : 1 x = 0, 7 y = 1, 8 n = 3 … 10 Figure 5 Interrupt Request (TyIR) Reload Reg.
C167CS-4R C167CS-L General Purpose Timer (GPT) Unit The GPT unit represents a very flexible multifunctional timer/counter structure which may be used for many different time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. The GPT unit incorporates five 16-bit timers which are organized in two separate modules, GPT1 and GPT2.
C167CS-4R C167CS-L T2EUD fCPU U/D 2n : 1 T2IN Interrupt Request (T2IR) GPT1 Timer T2 T2 Mode Control Reload Capture fCPU Interrupt Request (T3IR) 2n : 1 Toggle FF T3 Mode Control T3IN GPT1 Timer T3 T3OTL T3OUT U/D T3EUD Capture Reload T4IN fCPU 2n : 1 T4 Mode Control GPT1 Timer T4 Interrupt Request (T4IR) U/D T4EUD MCT04825 n = 3 … 10 Figure 6 Block Diagram of GPT1 With its maximum resolution of 8 TCL, the GPT2 module provides precise event control and time measurement.
C167CS-4R C167CS-L after the capture procedure. This allows the C167CS to measure absolute time differences or to perform pulse multiplication without software overhead. The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of GPT1 timer T3’s inputs T3IN and/or T3EUD. This is especially advantageous when T3 operates in Incremental Interface Mode.
C167CS-4R C167CS-L Real Time Clock The Real Time Clock (RTC) module of the C167CS consists of a chain of 3 divider blocks, a fixed 8:1 divider, the reloadable 16-bit timer T14, and the 32-bit RTC timer (accessible via registers RTCH and RTCL). The RTC module is directly clocked with the on-chip oscillator frequency divided by 32 via a separate clock driver (fRTC = fOSC/32) and is therefore independent from the selected clock generation mode of the C167CS. All timers count up.
C167CS-4R C167CS-L A/D Converter For analog signal measurement, a 10-bit A/D converter with 24 multiplexed input channels (16 standard channels and 8 extension channels) and a sample and hold circuit has been integrated on-chip. It uses the method of successive approximation. The sample time (for loading the capacitors) and the conversion time is programmable and can so be adjusted to the external circuitry.
C167CS-4R C167CS-L Serial Channels Serial communication with other microcontrollers, processors, terminals or external peripheral components is provided by two serial interfaces with different functionality, an Asynchronous/Synchronous Serial Channel (ASC0) and a High-Speed Synchronous Serial Channel (SSC). The ASC0 is upward compatible with the serial ports of the Infineon 8-bit microcontroller families and supports full-duplex asynchronous communication at up to 781 Kbit/s/ 1.03 Mbit/s/1.
C167CS-4R C167CS-L CAN-Modules The integrated CAN-Modules handle the completely autonomous transmission and reception of CAN frames in accordance with the CAN specification V2.0 part B (active), i.e. the on-chip CAN-Modules can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. The modules provide Full CAN functionality on up to 15 message objects each. Message object 15 may be configured for Basic CAN functionality.
C167CS-4R C167CS-L Parallel Ports The C167CS provides up to 111 I/O lines which are organized into eight input/output ports and one input port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O ports are true bidirectional ports which are switched to high impedance state when configured as inputs.
C167CS-4R C167CS-L Oscillator Watchdog The Oscillator Watchdog (OWD) monitors the clock signal generated by the on-chip oscillator (either with a crystal or via external clock drive). For this operation the PLL provides a clock signal which is used to supervise transitions on the oscillator clock. This PLL clock is independent from the XTAL1 clock. When the expected oscillator clock transitions are missing the OWD activates the PLL Unlock/OWD interrupt node and supplies the CPU with the PLL clock signal.
C167CS-4R C167CS-L Power Management The C167CS provides several means to control the power it consumes either at a given time or averaged over a certain timespan. Three mechanisms can be used (partly in parallel): • Power Saving Modes switch the C167CS into a special operating mode (control via instructions). Idle Mode stops the CPU while the peripherals can continue to operate. Sleep Mode and Power Down Mode stop all clock signals and all operation (RTC may optionally continue running).
C167CS-4R C167CS-L Instruction Set Summary Table 6 lists the instructions of the C167CS in a condensed way. The various addressing modes that can be used with a specific instruction, the operation of the instructions, parameters for conditional execution of instructions, and the opcodes for each instruction can be found in the “C166 Family Instruction Set Manual”. This document also provides a detailed description of each instruction.
C167CS-4R C167CS-L Table 6 Instruction Set Summary (cont’d) Mnemonic MOV(B) MOVBS MOVBZ JMPA, JMPI, JMPR JMPS J(N)B JBC JNBS CALLA, CALLI, CALLR CALLS PCALL TRAP PUSH, POP SCXT RET RETS RETP RETI SRST IDLE PWRDN SRVWDT DISWDT EINIT ATOMIC EXTR EXTP(R) EXTS(R) NOP Data Sheet Description Move word (byte) data Move byte operand to word operand with sign extension Move byte operand to word operand with zero extension Jump absolute/indirect/relative if condition is met Bytes 2/4 2/4 2/4 4 Jump absolute to
C167CS-4R C167CS-L Special Function Registers Overview Table 7 lists all SFRs which are implemented in the C167CS in alphabetical order. Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the Extended SFR-Space (ESFRs) are marked with the letter “E” in column “Physical Address”. Registers within on-chip X-peripherals are marked with the letter “X” in column “Physical Address”. An SFR can be specified via its individual mnemonic name.
C167CS-4R C167CS-L Table 7 C167CS Registers, Ordered by Name (cont’d) Name Physical Address C1UAR EFn2H X --- CAN1 Upper Arbitration Reg. (msg.
C167CS-4R C167CS-L Table 7 C167CS Registers, Ordered by Name (cont’d) Name Physical Address 8-Bit Description Addr. Reset Value CC17 FE62H 31H CAPCOM Register 17 0000H b F162H E B1H CAPCOM Reg. 17 Interrupt Ctrl. Reg. 0000H FE64H 32H CAPCOM Register 18 0000H b F164H E B2H CAPCOM Reg. 18 Interrupt Ctrl. Reg. 0000H FE66H 33H CAPCOM Register 19 0000H CC19IC b F166H E B3H CAPCOM Reg. 19 Interrupt Ctrl. Reg. 0000H CC1IC b FF7AH BDH CAPCOM Reg. 1 Interrupt Ctrl. Reg.
C167CS-4R C167CS-L Table 7 C167CS Registers, Ordered by Name (cont’d) Name Physical Address 8-Bit Description Addr. Reset Value CC30 FE7CH 3EH CAPCOM Register 30 0000H b F18CH E C6H CAPCOM Reg. 30 Interrupt Ctrl. Reg. 0000H FE7EH 3FH CAPCOM Register 31 0000H CC31IC b F194H E CAH CAPCOM Reg. 31 Interrupt Ctrl. Reg. 0000H CC3IC b FF7EH BFH CAPCOM Reg. 3 Interrupt Ctrl. Reg. 0000H FE88H 44H CAPCOM Register 4 0000H b FF80H C0H CAPCOM Reg. 4 Interrupt Ctrl. Reg.
C167CS-4R C167CS-L Table 7 Name C167CS Registers, Ordered by Name (cont’d) Physical Address 8-Bit Description Addr.
C167CS-4R C167CS-L Table 7 Name C167CS Registers, Ordered by Name (cont’d) Physical Address 8-Bit Description Addr. Reset Value ONES b FF1EH 8FH Constant Value 1’s Register (read only) FFFFH P0H b FF02H 81H Port 0 High Reg. (Upper half of PORT0) 00H P0L b FF00H 80H Port 0 Low Reg. (Lower half of PORT0) 00H FEA4H 52H Port 1 Digital Input Disable Register P1H b FF06H 83H Port 1 High Reg. (Upper half of PORT1) 00H P1L b FF04H 82H Port 1 Low Reg.
C167CS-4R C167CS-L Table 7 C167CS Registers, Ordered by Name (cont’d) Name Physical Address POCON4 F08CH E 46H Port P4 Output Control Register 0000H POCON6 F08EH E 47H Port P6 Output Control Register 0000H POCON7 F090H E 48H Port P7 Output Control Register 0000H POCON8 F092H E 49H Port P8 Output Control Register 0000H PP0 F038H E 1CH PWM Module Period Register 0 0000H PP1 F03AH E 1DH PWM Module Period Register 1 0000H PP2 F03CH E 1EH PWM Module Period Register 2 0000H
C167CS-4R C167CS-L Table 7 C167CS Registers, Ordered by Name (cont’d) Name Physical Address 8-Bit Description Addr. S0RBUF FEB2H 59H Serial Channel 0 Receive Buffer Reg.
C167CS-4R C167CS-L Table 7 C167CS Registers, Ordered by Name (cont’d) Name Physical Address T14 F0D2H E 69H RTC Timer 14 Register XXXXH T14REL F0D0H E 68H RTC Timer 14 Reload Register XXXXH T2 FE40H 20H GPT1 Timer 2 Register 0000H T2CON b FF40H A0H GPT1 Timer 2 Control Register 0000H T2IC b FF60H B0H GPT1 Timer 2 Interrupt Control Register 0000H FE42H 21H GPT1 Timer 3 Register 0000H T3CON b FF42H A1H GPT1 Timer 3 Control Register 0000H T3IC b FF62H B1H GPT1 Timer 3
C167CS-4R C167CS-L Table 7 Name XP3IC XPERCON ZEROS C167CS Registers, Ordered by Name (cont’d) Physical Address 8-Bit Description Addr. b F19EH E CFH RTC/PLL Interrupt Control Register 0000H F024H E 12H X-Peripheral Control Register 0401H b FF1CH 8EH Constant Value 0’s Register (read only) 0000H 1) The system configuration is selected during reset. 2) The reset value depends on the indicated reset source. Data Sheet Reset Value 47 V2.
C167CS-4R C167CS-L Absolute Maximum Ratings Table 8 Absolute Maximum Rating Parameters Parameter Symbol Limit Values Unit Notes min. max. TST TJ VDD -65 150 °C – -40 150 °C under bias -0.5 6.5 V – Voltage on any pin with respect to ground (VSS) VIN -0.5 VDD + 0.5 V – Input current on any pin during overload condition – -10 10 mA – Absolute sum of all input currents during overload condition – – |100| mA – Power dissipation PDISS – 1.
C167CS-4R C167CS-L Operating Conditions The following operating conditions must not be exceeded in order to ensure correct operation of the C167CS. All parameters specified in the following sections refer to these operating conditions, unless otherwise noticed. Table 9 Operating Condition Parameters Parameter Digital supply voltage Symbol VDD VSS IOV Overload current Absolute sum of overload Σ|IOV| Limit Values Unit Notes min. max. 4.5 5.5 V Active mode, fCPUmax = 40 MHz 2.51) 5.
C167CS-4R C167CS-L Parameter Interpretation The parameters listed in the following partly represent the characteristics of the C167CS and partly its demands on the system. To aid in interpreting the parameters right, when evaluating them for a design, they are marked in column “Symbol”: CC (Controller Characteristics): The logic of the C167CS will provide signals with the respective characteristics.
C167CS-4R C167CS-L DC Characteristics (cont’d) (Operating Conditions apply)1) Parameter Symbol Limit Values min. 6) RSTIN active current READY/RD/WR inact. current9) READY/RD/WR active current9) ALE inactive current9) ALE active current9) Port 6 inactive current9) Port 6 active current9) PORT0 configuration current10) XTAL1 input current Pin capacitance11) (digital inputs/outputs) IRSTH7) IRSTL8) IRWH7) IRWL8) IALEL7) IALEH8) IP6H7) IP6L8) IP0H7) IP0L8) IIL CC CIO CC max. ±500 nA 0.
C167CS-4R C167CS-L Table 10 Current Limits for Port Output Drivers Port Output Driver Maximum Output Current (IOLmax, -IOHmax)1) Nominal Output Current (IOLnom, -IOHnom) P2.7 - P2.0 10 mA 2.5 mA (PORT0, PORT1, ----Port 4, ALE, RD, WR, BHE, CLKOUT, RSTOUT, RSTIN2)) 2.5 mA All other outputs 1.6 mA ----- 1) An output current above |IOXnom| may be drawn from up to three pins (P2.7-P2.0 only) at the same time.
C167CS-4R C167CS-L I [µA] IIDOmax IIDOtyp 3000 IPDRmax 2000 1000 IPDOmax 10 Figure 9 Data Sheet 20 30 40 fOSC [MHz] Idle and Power Down Supply Current as a Function of Oscillator Frequency 53 V2.
C167CS-4R C167CS-L IDD5max I [mA] 140 IDD5typ 120 100 80 IIDX5max IIDX5typ 60 40 20 10 Figure 10 Data Sheet 20 30 40 fCPU [MHz] Supply/Idle Current as a Function of Operating Frequency 54 V2.
C167CS-4R C167CS-L AC Characteristics Definition of Internal Timing The internal operation of the C167CS is controlled by the internal CPU clock fCPU. Both edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles) operations. The specification of the external timing (AC Characteristics) therefore depends on the time between two consecutive edges of the CPU clock, called “TCL” (see Figure 11).
C167CS-4R C167CS-L P0.15-13 (P0H.7-5). Register RP0H can be loaded from the upper half of register RSTCON under software control. Table 11 associates the combinations of these three bits with the respective clock generation mode. Table 11 C167CS Clock Generation Modes CLKCFG CPU Frequency (RP0H.7-5) fCPU = fOSC × F 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 fOSC × 4 fOSC × 3 fOSC × 2 fOSC × 5 fOSC × 1 fOSC × 1.5 fOSC / 2 fOSC × 2.5 External Clock Input Range1) Notes 2.
C167CS-4R C167CS-L Due to this adaptation to the input clock the frequency of fCPU is constantly adjusted so it is locked to fOSC. The slight variation causes a jitter of fCPU which also effects the duration of individual TCLs. The timings listed in the AC Characteristics that refer to TCLs therefore must be calculated using the minimum TCL that is possible under the respective circumstances. The actual minimum value for TCL depends on the jitter of the PLL.
C167CS-4R C167CS-L Direct Drive When direct drive is configured (CLKCFG = 011B) the on-chip phase locked loop is disabled and the CPU clock is directly driven from the internal oscillator with the input clock signal. The frequency of fCPU directly follows the frequency of fOSC so the high and low time of fCPU (i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock fOSC.
C167CS-4R C167CS-L AC Characteristics External Clock Drive XTAL1 (Operating Conditions apply) Table 12 External Clock Drive Characteristics Parameter Symbol Direct Drive 1:1 min. Oscillator period High time2) 2) Low time Rise time 2) 2) Fall time tOSC t1 t2 t3 t4 Prescaler 2:1 PLL 1:N Unit max. min. max. min. max.
C167CS-4R C167CS-L A/D Converter Characteristics (Operating Conditions apply) Table 13 A/D Converter Characteristics Parameter Symbol Limit Values min.
C167CS-4R C167CS-L 5) As the default basic clock after reset is fBC = fCPU / 4 the ADC’s prescaler (ADCTC) must be programmed to a valid factor as early as possible. A timeframe of approx. 6000 CPU clock cycles is sufficient to ensure a proper reset calibration. This corresponds to minimum 300 instructions (worst case: external MUX bus with maximum waitstates). This is required for fCPU > 33 MHz and is recommended for fCPU > 25 MHz.
C167CS-4R C167CS-L Testing Waveforms 2.4 V 1.8 V 1.8 V Test Points 0.8 V 0.8 V 0.45 V AC inputs during testing are driven at 2.4 V for a logic ’1’ and 0.45 V for a logic ’0’. Timing measurements are made at VIH min for a logic ’1’ and VIL max for a logic ’0’. MCA04414 Figure 14 Input Output Waveforms VLoad + 0.1 V VOH - 0.1 V Timing Reference Points VLoad - 0.1 V VOL + 0.
C167CS-4R C167CS-L AC Characteristics Table 15 CLKOUT Reference Signal Parameter Symbol Limits min. tc5 tc6 tc7 tc8 tc9 CLKOUT cycle time CLKOUT high time CLKOUT low time CLKOUT rise time CLKOUT fall time 1) CC Unit max. 40/30/251) ns CC 8 – ns CC 6 – ns CC – 4 ns CC – 4 ns The CLKOUT cycle time is influenced by the PLL jitter (given values apply to fCPU = 25/33/40 MHz). For a single CLKOUT cycle (2 TCL) the deviation caused by the PLL jitter is below 1 ns (for fCPU > 25 MHz).
C167CS-4R C167CS-L Table 17 External Bus Cycle Timing (Operating Conditions apply) Parameter Symbol Limits min. Output delay from CLKOUT falling edge tc10 CC 0 Valid for: address (MUX on PORT0), write data out Unit max.
C167CS-4R C167CS-L The bandwidth of a parameter (minimum and maximum value) covers the whole operating range (temperature, voltage) as well as process variations. Within a given device, however, this bandwidth is smaller than the specified range. This is also due to interdependencies between certain parameters. Some of these interdependencies are described as relative timing (see below) or in additional notes (see standard timing).
C167CS-4R C167CS-L CLKOUT Normal ALE Cycle tc 11 tc 11 Normal ALE Extended ALE Cycle tc 19 tc 19 Extended ALE tc 19 tc 19 tc 11 tc 11 CSxE, CSxL tc16 tc16 tc17 A23-A0, BHE Valid tc12 tc 12 tc12 WRL, WRH, WR, WrCS tc12 1) 2) tc10 tc20 tc21 Data OUT D15-D0 3) MCTC Note: Write data is deactivated 1 TCL earlier if early write is enabled (same timing). Figure 17 Data Sheet tc18 4) MTTC MCT04435 Demultiplexed Bus, Write Access 66 V2.
C167CS-4R C167CS-L CLKOUT Normal ALE Cycle tc 11 tc 11 Normal ALE Extended ALE Cycle tc 19 tc 19 Extended ALE tc 19 tc 19 tc 11 tc 11 CSxE, CSxL tc16 tc16 tc17 A23-A0, BHE Valid tc13 tc13 RD, RdCS tc13 1) tc15 tc14 D15-D0 Data IN 3) MCTC 4) MTTC MCT04436 Figure 18 Data Sheet Demultiplexed Bus, Read Access 67 V2.
C167CS-4R C167CS-L CLKOUT Normal ALE Cycle tc 11 tc 11 Normal ALE Extended ALE Cycle tc 19 tc 19 Extended ALE tc 19 tc 19 tc 11 tc 11 CSxE, CSxL tc16 tc16 tc17 A23-A16, BHE Valid tc12 tc 12 tc12 WRL, WRH, WR, WrCS 1) tc 10 AD15-AD0 (Normal ALE) 2) tc 10 tc 21 tc 20 tc 17 tc 18 Low Address tc 10 Data OUT tc 10 tc 20 tc 17 tc 21 AD15-AD0 (Extended ALE) tc12 Low Address tc 18 Data OUT 3) MCTC Note: Write data is deactivated 2 TCL earlier if early write is enabled (same timi
C167CS-4R C167CS-L CLKOUT Normal ALE Cycle tc 11 tc 11 Normal ALE Extended ALE Cycle tc 19 tc 19 Extended ALE tc 19 tc 19 tc 11 tc 11 CSxE, CSxL tc16 tc16 tc17 A23-A16, BHE Valid tc13 tc13 RD, RdCS tc13 1) tc10 tc20 tc21 AD15-AD0 (Normal ALE) tc17 tc14 Low Address tc10 Data IN tc20 tc21 AD15-AD0 (Extended ALE) tc15 tc15 tc17 tc14 Low Address Data IN 3) MCTC 4) MTTC MCT04438 Figure 20 Data Sheet Multiplexed Bus, Read Access 69 V2.
C167CS-4R C167CS-L Bus Cycle Control via READY Input The duration of an external bus cycle can be controlled by the external circuitry via the READY input signal. Synchronous READY permits the shortest possible bus cycle but requires the input signal to be synchronous to the reference signal CLKOUT. Asynchronous READY puts no timing constraints on the input signal but incurs one waitstate minimum due to the additional synchronization stage.
C167CS-4R C167CS-L Running Cycle 1) READY WS MUX/MTTC 2) CLKOUT tc 15 tc 14 Data IN tc 10 tc 18 tc 21 D15-D0 tc 20 The next external bus cycle may start here. D15-D0 Data OUT tc 13 tc 12 tc 13 / tc 19 Command (RD, WR) 3) tc 26 tc 25 Synchronous READY tc 26 Asynchronous READY 3) Figure 21 Data Sheet tc 25 4) tc 25 4) tc 26 4) tc 27 tc 26 tc 25 4) 5) MCT04820 READY Timing 71 V2.
C167CS-4R C167CS-L External Bus Arbitration Table 20 Bus Arbitration Timing (Operating Conditions apply) Parameter Symbol HOLD input setup time to CLKOUT falling edge CLKOUT to BREQ delay CLKOUT to HLDA delay CSx release1) CSx drive Other signals release1) Other signals drive1) 1) tc28 tc29 tc30 tc31 tc32 tc33 tc34 Limit Values Unit min. max.
C167CS-4R C167CS-L CLKOUT tc 28 HOLD tc 30 HLDA 1) tc 29 2) BREQ tc 31 CS 3) tc 33 Other Signals MCT04421 Figure 22 External Bus Arbitration, Releasing the Bus Notes 1) The C167CS will complete the currently running bus cycle before granting bus access. 2) This is the first possibility for BREQ to get active. 3) The CS outputs will be resistive high (pullup) after t33. Latched CS outputs are driven high for 1 TCL before the output drivers are switched off. Data Sheet 73 V2.
C167CS-4R C167CS-L CLKOUT 5) tc 28 HOLD tc 30 HLDA tc 29 tc 29 tc 29 4) BREQ tc 32 CS tc 34 Other Signals MCT04422 Figure 23 External Bus Arbitration, (Regaining the Bus) Notes 4) This is the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated earlier, the regain-sequence is initiated by HOLD going high. Please note that HOLD may also be deactivated without the C167CS requesting the bus. 5) The next C167CS driven bus cycle may start here.
C167CS-4R C167CS-L External XRAM Access If XPER-Share mode is enabled the on-chip XRAM of the C167CS can be accessed (during hold states) by an external master like an asynchronous SRAM. Table 21 XRAM Access Timing (Operating Conditions apply) Parameter Symbol Limit Values min.
C167CS-4R C167CS-L Package Outlines GPM09391 P-MQFP-144-6 (Plastic Metric Quad Flat Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Data Sheet 76 Dimensions in mm V2.
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