Datasheet

C167CS-4R
C167CS-L
Data Sheet 64 V2.2, 2001-08
Table 17 External Bus Cycle Timing (Operating Conditions apply)
Parameter Symbol Limits Unit
min. max.
Output delay from CLKOUT falling edge
Valid for: address (MUX on PORT0), write data out
tc
10
CC 0 14 ns
Output delay from CLKOUT edge
Valid for: latched CS
, ALE (normal)
tc
11
CC -3 6 ns
Output delay from CLKOUT edge
Valid for: WR
, WRL, WRH, WrCS
tc
12
CC -4 7 ns
Output delay from CLKOUT edge
Valid for: RD
, RdCS
tc
13
CC -2 7 ns
Input setup time to CLKOUT falling edge
Valid for: read data in
tc
14
SR 10 – ns
Input hold time after CLKOUT falling edge
Valid for: read data in
1)
tc
15
SR 0 – ns
Output delay from CLKOUT falling edge
Valid for: address (on PORT1 and/or P4), BHE
tc
16
CC 0 9
2)
ns
Output hold time after CLKOUT falling edge
Valid for: address, BHE
3)
tc
17
CC -2 8 ns
Output hold time after CLKOUT edge
4)
Valid for: write data out
tc
18
CC -1 – ns
Output delay from CLKOUT falling edge
Valid for: ALE (extended), early CS
tc
19
CC -4 4 ns
Turn off delay after CLKOUT edge
4)
Valid for: write data out
tc
20
CC – 7ns
Turn on delay after CLKOUT falling edge
4)
Valid for: write data out
tc
21
CC -5 – ns
Output hold time after CLKOUT edge
Valid for: early CS
tc
22
CC -6 4 ns
1)
Read data are latched with the same (internal) clock edge that triggers the address change and the rising edge
of RD
. Therefore address changes before the end of RD have no impact on (demultiplexed) read cycles.
2)
If the capacitive load on the respective output pins is limited to 30 pF the maximum output delay tc
16
can be
reduced to 8 ns.
3)
Due to comparable propagation delays the address does not change before WR goes high. The minimum
output delay (
tc
17min
) is therefore the actual value of tc
12
.
4)
Not 100% tested, guaranteed by design and characterization.