Datasheet

C167CS-4R
C167CS-L
Data Sheet 75 V2.2, 2001-08
External XRAM Access
If XPER-Share mode is enabled the on-chip XRAM of the C167CS can be accessed
(during hold states) by an external master like an asynchronous SRAM.
Figure 24 External Access to the XRAM
Table 21 XRAM Access Timing (Operating Conditions apply)
Parameter Symbol Limit Values Unit
min. max.
Address setup time before RD
/WR falling edge t
40
SR 4 – ns
Address hold time after RD
/WR rising edge t
41
SR 0 – ns
Data turn on delay after RD
falling edge
Read
t
42
CC 2 – ns
Data output valid delay after address latched
t
43
CC – 37 ns
Data turn off delay after RD
rising edge t
44
CC 0 10 ns
Write data setup time before WR
rising edge
Write
t
45
SR 10 – ns
Write data hold time after WR
rising edge t
46
SR 1 – ns
WR
pulse width t
47
SR 18 – ns
WR
signal recovery time t
48
SR t
40
– ns
Read Data
43
t
42
t
44
t
MCT04423
(RD, WR)
Write Data
Command
Address
40
t
45
t
47
t
46
t
48
t
41
t