Datasheet

ManualsBrandsINFINEON TECHNOLOGIES ManualsVoltage RegulatorsTLE4299G V33

Datasheet 1 Rev. 1.1, 2007-10-17

Low-Drop Fixed Voltage Regulator TLE 4299

Type Package

TLE 4299 GV33 PG-DSO-8-16

TLE 4299 GMV33 PG-DSO-14-30

P-DSO-8-3

P-DSO-14-3, -8, -9, -11

Features

• Output voltage 3.3V ± 2%

• 150 mA Output current

• Extreme low current consumption in ON state

• Inhibit function: Below 1 µA current consumption

in off mode

• Early warning

• Reset output low down to

= 1 V

• Overtemperature protection

• Reverse polarity proof

• Wide temperature range

• Green Product (RoHS compliant)

• AEC Qualified

Functional Description

The TLE 4299 is a monolithic voltage regulator with fixed

5-V (see data sheet TLE4299G/GM) or 3.3 V output,

supplying loads up to 150 mA. It is especially designed

for applications that may not be powered down while the

motor is off. In addition the TLE 4299GMV includes an inhibit function. When the inhibit

signal is removed, the device is switched off and the quiescent current is less than 1 µA.

To achieve proper operation of the µ-controller, the device supplies a reset signal. The

reset delay time is selected application-specific by an external delay capacitor. The reset

threshold is adjustable. An early warning signal supervises the voltage at pin SI. The

TLE 4299 is pin-compatible to the TLE 4269 and functional similar with the additional

inhibit function. The TLE 4299 is designed to supply microcontroller systems even under

automotive environment conditions. Therefore it is protected against overload, short

circuit and over temperature.

Summary of content (25 pages)

PAGE 1
Low-Drop Fixed Voltage Regulator TLE 4299 Features • • • • • • • • • • • Output voltage 3.
PAGE 2
TLE 4299 Circuit Description The TLE 4299 is a PNP based very low drop linear voltage regulator. It regulates the output voltage to VQ = 3.3 V for an input voltage range of 4.4 V ≤ VI ≤ 45 V. The control circuit protects the device against potential damages caused by overcurrent and overtemperature. The internal control circuit achieves a 3.3 V output voltage with a tolerance of ± 2%.
PAGE 3
TLE 4299 TLE 4299 I Q Current and Saturation Control BandGapReference RSO RRO SO SI Reference RO Reset Control RADJ D GND AEB03103 Figure 1 Datasheet Block Diagram TLE 4299 GV33 3 Rev. 1.
PAGE 4
TLE 4299 TLE 4299 I Q Current and Saturation Control BandGapReference INH RSO RRO Inhibit Control SO SI Reference RO Reset Control RADJ D GND AEB03104 Figure 2 Datasheet Block Diagram TLE 4299 GMV33 4 Rev. 1.
PAGE 5
TLE 4299 PG-DSO-8-16 I 1 8 Q SI 2 7 SO RADJ 3 6 RO D 4 5 GND AEP02832 Figure 3 Pin Configuration (top view) Pin Definitions and Functions (TLE 4299 GV33) Pin No. Symbol Function 1 I Input; block directly to GND on the IC with a ceramic capacitor. 2 SI Sense Input; if not needed connect to Q. 3 RADJ Reset Threshold Adjust; if not needed connect to GND. 4 D Reset Delay; to select delay time, connect to GND via external capacitor.
PAGE 6
TLE 4299 PG-DSO-14-30 RADJ 1 14 SI D 2 13 I GND 3 12 GND GND 4 11 GND GND 5 10 GND INH 6 9 Q RO 7 8 SO AEP02831 Figure 4 Pin Configuration (top view) Pin Definitions and Functions (TLE 4299 GMV33) Pin No. Symbol Function 1 RADJ Reset Threshold Adjust; if not needed connect to GND. 2 D Reset Delay; connect to GND via external delay capacitor for setting delay time.
PAGE 7
TLE 4299 Absolute Maximum Ratings Tj = – 40 to 150 °C Parameter Symbol Limit Values Unit Notes min. max. VI – 40 45 V – VINH – 40 45 V – VSI ISI – 0.3 45 V – -1 1 mA – VRADJ IRADJ – 0.3 7 V – -10 10 mA – VD – 0.3 7 V – VR – 0.3 7 V – VSO – 0.3 7 V – VQ IQ – 0.
PAGE 8
TLE 4299 Absolute Maximum Ratings (cont’d) Tj = – 40 to 150 °C Parameter Symbol Limit Values Unit Notes min. max. Tj TStg – 150 °C – – 50 150 °C – VI Tj 4.
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TLE 4299 Characteristics VI = 13.5 V; Tj = – 40 °C < Tj < 150 °C Parameter Symbol Limit Values Unit Measuring Condition min. typ. max. Output voltage VQ 3.23 3.30 3.37 V 1 mA ≤ IQ ≤ 100 mA; 5.5 V ≤ VI ≤ 16 V Output voltage VQ 3.20 3.30 3.40 V IQ ≤ 150 mA; 5.
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TLE 4299 Characteristics (cont’d) VI = 13.5 V; Tj = – 40 °C < Tj < 150 °C Parameter Symbol Limit Values Unit Measuring Condition min. typ. max. Reset Generator Switching threshold Vrt Reset threshold headroom VRTHEAD 50 Reset pull up RRO Reset low voltage External reset pull up V – 200 300 mV – 10 20 kΩ – VR – 0.17 0.40 V VQ < 3.0 V; internal RRO; IR = 1 mA VR ext 5.6 – kΩ Pull up resistor Q 1.6 1.85 2.35 V – Delay switching threshold VDT 3.00 3.10 3.
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TLE 4299 Characteristics (cont’d) VI = 13.5 V; Tj = – 40 °C < Tj < 150 °C Parameter Symbol Limit Values Unit Measuring Condition min. typ. max. – 2.4 4.0 µs RSO ext = 5.6kΩ tpd SO HL – 2.5 6.0 µs RSO ext = 5.6kΩ Sense high reaction time tpd SO LH Sense low reaction time Note: The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread.
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TLE 4299 Application Information TLE 4299 VBAT CI2 P CQ1 C Q 22 F Q2 I CI1 Current and Saturation Control BandGapReference RSO RRO SO RSI1 SI RO Reference RSI2 Reset Control RADJ1 RADJ GND D RADJ2 CD AES03105 Figure 6 Datasheet Application Diagram TLE 4299 GV33 12 Rev. 1.
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TLE 4299 TLE 4299 VBAT CI2 P CQ1 C Q 22 F Q2 I CI1 BandGapReference From KI. 15 INH Current and Saturation Control Inhibit Logic RSO RRO SO RSI1 SI RO Reference RSI2 Reset Control RADJ1 RADJ GND D RADJ2 CD AES03106 Figure 7 Application Diagram with Inhibit Function TLE4299 GMV33 The TLE 4299 supplies a regulated 3.3 V output voltage with an accuracy of 2% for an input voltage between 4.
PAGE 14
TLE 4299 Reset The power on reset feature is necessary for a defined start of the microprocessor when switching on the application. For the reset delay time after the output voltage of the regulator is above the reset threshold, the reset signal is set High again. The reset delay time is defined by the reset delay capacitor CD at pin D. The under-voltage reset circuitry supervises the output voltage. In case VQ decreases below the reset threshold the reset output is set LOW after the reset reaction time.
PAGE 15
TLE 4299 VI t VQ < t RR V RT dV I D = dt C D VD t V DT V ST V RO t RR td t VRO, SAT t Power-on-Reset Figure 8 Thermal Shutdown Voltage Dip at Input Undervoltage Secondary Spike Overload at Output AED03107 Reset Timing Diagram The reset output is an open collector output. An external pull-up can be added with a resistor value of at least 5.6 kΩ. In addition the reset switching threshold can be adjusted by an external voltage divider.
PAGE 16
TLE 4299 Early Warning The early warning function compares a voltage defined by the user to an internal reference voltage. Therefore the supervised voltage has to be scaled down by an external voltage divider in order to compare it to the internal sense threshold of typical 1.36 V. The sense output pin is set low, when the voltage at SI falls below this threshold.
PAGE 17
TLE 4299 Current Consumption Iq versus Junction Temperature Tj Current Consumption Iq versus Output Current IQ Iq [µA] 2_IQ-IQ.VSD 12 1_Iq-Tj.vsd Iq [mA] VI = 13.5V 100 IQ = 1mA 10 8 Tj = 150 °C 6 Tj = 25 °C 4 Tj = -40 °C 1 2 0.01 -40 -20 0 40 0 20 40 60 80 100 120 140 80 120 160 Tj [°C] Current Consumption Iq versus Input Voltage VI Output Voltage VQ versus Junction Temperature Tj 3_IQ-VI.VSD 3 AED01671 3.5 T = 25°C Iq [mA] IQ [mA] VQ V 3.4 V Ι = 13.5 V 2 3.3 1.5 3.
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TLE 4299 Reverse Output Current IQ versus Output Voltage VQ Maximum Output Current IQ versus Junction Temperature Tj 8_IQMAX-TJ.VSD 550 10_IQ-VQ.vsd 10 VI = 0 V IQ [mA] IQ [mA] -20 Tj = -40 °C VI = 13.
PAGE 19
TLE 4299 Power Supply Ripple Rejection PSRR versus Frequency f Region of Stability 12_ESRIQ_150.VSD 100 CQ = 22µF Tj = 150 °C ESRCQ [Ω] 13_PSRR.VSD 90 PSRR [dB] VI=6V 10 IQ = 0.1 mA VI=25V 70 IQ = 1 mA 1 60 Stable Region VI=25V 0.1 40 0.01 0 40 IQ = 10 mA 50 VI=6V 80 120 VRIPPLE = 0.5 V VIN = 13.5 V CQ = 22 µF Tantalum Tj = 25 °C 100 10 160 1k IQ = 100 mA 100k 10k f [Hz] IQ [mA] Load Transient Response Peak Voltage DVQ Region of Stability 12_ESR-IQ_40.
PAGE 20
TLE 4299 Inhibit Input Current at Input Voltage Extremes (INH=OFF) Line Transient Response Peak Voltage DVQ 25_IINH vs VIN INH_off.vsd IINH 21_Line Trancient vs time 125.vsd [µA] 50 Tj=125°C Vi=13.5V dVI 2V INH = OFF 40 30 Tj = -40...150°C VQ 20 10 T=500µs/DIV VQ=50mV/DIV 10 20 30 40 VIN [V] Reset Trigger Threshold VRT versus Junction Temperature Tj Inhibut Input Current IINH at Inhibit Input Voltage Extremes 24_IINH vs VINH.vsd 26_VRT VS TEMP.VSD 3.25 IINH VI = 13.
PAGE 21
TLE 4299 Sense Threshold High versus Junction Temperature Tj Reset Delay Time TRD versus Junction Temperature Tj 27_RESETDELAY VS TEMP.VSD 60 VI = 13.5 V TRD [V] 1.50 CD = 100nF 45 1.45 40 1.40 35 1.35 -40 -20 0 VI = 13.5 V VSI_Hi [ms] 50 34_VSI_HI VS TEMP.VSD 1.60 -40 -20 20 40 60 80 100 120 140 0 Tj [°C] Tj [°C] Sense Threshold Low versus Junction Temperature Tj Delay Capacitor Charge Current versus Junction Temperature Tj 27A_ID-TEMP.VSD 6 [V] 4 1.40 3 1.35 2 1.
PAGE 22
TLE 4299 Package Outlines PG-DSO-8-16 (SMD) (Plastic Dual Small Outline) 0.1 2) 0.41+0.1 -0.06 0.2 8 5 1 4 5 -0.2 1) M B 0.19 +0.06 C 8 MAX. 1.27 4 -0.21) 1.75 MAX. 0.175 ±0.07 (1.45) 0.35 x 45˚ 0.64 ±0.25 6 ±0.2 A B 8x 0.2 M C 8x A Index Marking 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Lead width can be 0.61 max.
PAGE 23
TLE 4299 PG-DSO-14-30 (SMD) (Plastic Dual Small Outline) 1.75 MAX. C 1) 4 -0.2 B 1.27 0.64 ±0.25 0.1 2) 0.41+0.10 -0.06 6±0.2 0.2 M A B 14x 14 0.2 M C 8 1 7 1) 8.75 -0.2 8˚MAX. 0.19 +0.06 0.175 ±0.07 (1.47) 0.35 x 45˚ A Index Marking 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Lead width can be 0.61 max.
PAGE 24
TLE 4299 Revision History Version Date Rev. 1.1 2007-10-17 Initial version of RoHS-compliant derivate of TLE 4299 Page 1: AEC certified statement added Page 1 and Page 22f: RoHS compliance statement and Green product feature added Page 1 and Page 22f: Package drawing changed to RoHS compliant version Legal Disclaimer updated Datasheet Changes 24 Rev. 1.
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Edition 2007-10-17 Published by Infineon Technologies AG 81726 Munich, Germany © 2007 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics.