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Data Sheet TLE 6230 GP

V2.3 Page 18. Nov. 2009

Smart Octal Low-Side Switch

Features

Product Summary

• Short Circuit Protection

• Overtemperature Protection

• Overvoltage Protection

• 16 bit Serial Data Input and Diagnos-

tic Output (2 bit/ch. acc. SPI protocol)

• Direct Parallel Control of Four Channels for PWM Applications

• Parallel Inputs High or Low Active Programmable

• General Fault Flag

• Low Quiescent Current

• Compatible with 3,3 V Micro Controllers

• Electostatic Discharge (ESD) Protection

• Green Product (RoHS compliant)

• AEC Qualified

Application

• µC Compatible Power Switch for 12 V and 24V Applications

• Switch for Automotive and Industrial Systems

• Solenoids, Relays and Resistive Loads

• Robotic Controls

General description

Octal Low-Side Switch in Smart Power Technology (SPT) with a Serial Peripheral Interface (SPI) and

eight open drain DMOS output stages. The TLE 6230 GP is protected by embedded protection func-

tions and designed for automotive and industrial applications. The output stages are controlled via an

SPI Interface. Additionally four channels can be controlled direct in parallel for PWM applications.

Therefore the TLE 6230 GP is particularly suitable for engine management and powertrain systems.

RESET FAULT

Output Stage

Output Control

Buffer

Serial Interface

SPI

LOGIC

SCLK

GND

IN1

IN2

IN3

IN4

OUT1

OUT8

PRG

as Ch. 1

GND

Protection

Functions

Supply voltage V

4.5 – 5.5 V

Drain source clamping voltage V

DS(AZ)max

55 V

On resistance R

0.75 Ω

Output current (all outp.ON equal) I

D(NOM)

500 mA

(individually) 1 A

PG-DSO 36

Summary of content (16 pages)

PAGE 1
Data Sheet TLE 6230 GP Smart Octal Low-Side Switch Supply voltage Drain source clamping voltage On resistance Output current (all outp.ON equal) (individually) Features Product Summary • Short Circuit Protection • Overtemperature Protection • Overvoltage Protection • 16 bit Serial Data Input and Diagnostic Output (2 bit/ch. acc.
PAGE 2
Data Sheet TLE 6230 GP Block Diagram Detailed Block Diagram RESET FAULT VS Channel 1 Normal function GND VS SCB/Overload PRG Open load short to ground IN1 & Output Stage OUT1 IN2 IN3 IN4 SO SI SCLK & Channel 2 OUT2 & Channel 3 OUT3 & Channel 4 OUT4 Channel 5 OUT5 Channel 6 OUT6 Channel 7 OUT7 Channel 8 OUT8 SPI Interface 16 bit CS GND V2.3 Page 2 18. Nov.
PAGE 3
Data Sheet TLE 6230 GP Pin Description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Symbol GND NC NC OUT1 OUT2 IN1 IN2 VS RESET CS PRG IN3 IN4 OUT3 OUT4 NC NC GND GND NC NC OUT5 OUT6 NC NC FAULT SO SCLK SI NC NC OUT7 OUT8 NC NC GND Pin Configuration (Top view) Function Ground not connected not connected Power Output Channel 1 Power Output Channel 2 Input Channel 1 Input Channel 2 Supply Voltage Reset Chip Select Program (inputs high or low-activ
PAGE 4
Data Sheet TLE 6230 GP Maximum Ratings for Tj = – 40°C to 150°C Parameter Supply Voltage Symbol VS Continuous Drain Source Voltage (OUT1...OUT8) VDS Input Voltage, All Inputs and Data Lines VIN Values -0.3 ... + 7 Unit V 40 V - 0.3 ... + 7 V 2) Load Dump Protection VLoad Dump = UP+US; UP=13.
PAGE 5
Data Sheet TLE 6230 GP Electrical Characteristics Parameter and Conditions VS = 4.5 to 5.5 V ; Tj = - 40 °C to + 150 °C ; Reset = H (unless otherwise specified) Symbol Values min Unit typ max 1. Power Supply, Reset Supply Voltage4 Supply Current (outputs ON) VS 4.5 -- 5.5 IS(ON) -- 1 2 mA IS(OFF) -- 1 2 mA tReset,min 10 -- -- µs TJ = 25°C TJ = 150°C RDS(ON) --- 0.8 -- 1 1.7 Ω Output OFF VDS(AZ) 40 -- 55 V ID(lim) 1 1.
PAGE 6
Data Sheet TLE 6230 GP Electrical Characteristics cont. Parameter and Conditions Symbol VS = 4.5 to 5.5 V ; Tj = - 40 °C to + 150 °C ; Reset = H (unless otherwise specified) Values Unit min typ max 5. Diagnostic Functions Open Load Detection Voltage VDS(OL) VS -2.5 VS -2 VS -1.3 V Output Pull Down Current IPD(OL) 50 90 150 µA Fault Delay Time td(fault) 50 100 200 µs Short to Ground Detection Voltage VDS(SHG) Short to Ground Detection Current ISHG -50 -100 -150 µA ID(lim) 1...
PAGE 7
Data Sheet TLE 6230 GP Functional Description The TLE 6230 GP is an octal-low-side power switch which provides a serial peripheral interface (SPI) to control the 8 power DMOS switches, as well as diagnostic feedback. The power transistors are protected against short to VBB, overload, overtemperature and against overvoltage by an active zener clamp. The diagnostic logic recognizes a fault condition which can be read out via the serial diagnostic output (SO).
PAGE 8
Data Sheet TLE 6230 GP Power Transistor Protection Functions8) Each of the eight output stages has its own zener clamp, which causes a voltage limitation at the power transistor when solenoid loads are switched off. The outputs are provided with a current limitation set to a minimum of 1 A. The continuous current for each channel is 500 mA (all channels ON). Each output is protected by embedded protection functions.
PAGE 9
Data Sheet TLE 6230 GP high level at this pin (within the data byte) will switch on the power switch, provided that the corresponding parallel input is also switched on (AND-operation for channel 1 to 4). SO - Serial Output. Diagnostic data bits are shifted out serially at this pin, the most significant bit first. SO is in a high impedance state until the CS pin goes to a logic low state. New diagnostic data will appear at the SO pin following the rising edge of SCLK. RESET - Reset pin.
PAGE 10
Data Sheet TLE 6230 GP A definite distinction between open load and short to ground is guaranteed by design. The standard way of obtaining diagnostic information is as follows: Clock in serial information into SI pin and wait approximately 150 µs to allow the outputs tosettle. Clock in the identical serial information once again - during this process the data coming out at SO contains the bit combinations representing the diagnosis conditions as described in figure 1.
PAGE 11
Data Sheet TLE 6230 GP Timing Diagrams CS SCLK C SI O N T R O L Byte 7 6 5 4 13 12 11 10 9 8 7 6 5 4 3 2 1 2 1 MSB 15 SO 0 LSB 14 3 0 Figure 2: Serial Interface Figure 3: Input Timing Diagram CS 0.7VS tdt 0.2 VS tlag tSCKH SCLK tlead 0.7VS 0.2VS tSCKL tSU tH 0.7VS SI 0.2VS Figure 4: 0.7 VS SCLK CS 0.2 VS tvalid tDis SO 0.7 VS SO 0.2 VS SO 0.7 VS 0.2 VS SO Valid Time Waveforms V2.3 Enable and Disable Time Waveforms Page 11 18. Nov.
PAGE 12
Data Sheet TLE 6230 GP VIN t tOFF tON VDS 80% 20% t Figure 5: Power Outputs Timing is valid for resistive load with parallel and serial control. Rising edge of chip select initiates the switching Application Circuits VBB VS = 5V C 10k VS PRG OUT1 FAULT OUT2 RESET IN1 µC e.g. C167 V2.3 IN2 IN3 IN4 MTSR SI MRST SO CLK CLK P xy CS TLE 6230 GP OUT8 GND Page 12 18. Nov.
PAGE 13
Data Sheet TLE 6230 GP Typical electrical Characteristics Drain-Source on-resistance RDS(ON) = f (Tj) ; Vs = 5V Channel 1-8 Typical Drain- Source ON-Resistance 1,5 1,4 1,3 RDS(ON) [Ohm] 1,2 1,1 1 0,9 0,8 0,7 0,6 0,5 0,4 -50 -25 0 25 50 75 100 125 150 175 Tj[°C] Figure 6 : Typical ON Resistance versus Junction-Temperature Channel 1-8 Output Clamping Voltage VDS(AZ) = f (Tj) ; Vs = 5V Channel 1-8 Typical Clamping Voltage 45 VDS(AZ) [V] 44 43 42 41 -50 -25 0 25 50 75 100 125 150
PAGE 14
Data Sheet TLE 6230 GP Maximum single clamp Energy TLE 6230, single Clamp, linear Current Ramp Maximum Energy Rating @ Tj=150°C 300 250 200 150 100 50 0 0 0,2 0,4 0,6 0,8 1 1,2 1,4 Peak current [A] Maximum Clamp Energy (single event) versus Peak Current Figure 8 : Channel 1-8 Parallel SPI Configuration Injector 1 4 P x.1-4 MTSR 4 PW M Channels SI SO CLK CS CS MRST CLK P x.y 4 SI SO C167 CLK P x.y Injector 3 TLE 6220 GP Quad Injector 4 4 PW M Channels P x.
PAGE 15
Data Sheet TLE 6230 GP Package and Ordering Code (all dimensions in mm) PG-DSO 36 TLE 6230 GP V2.3 Page 15 18. Nov.
PAGE 16
Data Sheet TLE 6230 GP Edition 2008-04-17 Published by Infineon Technologies AG 81726 Munich, Germany © 2008 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics.