Datasheet

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AENEON™ Data Sheet 1 Revision 1.10, 2008-05

A Qimonda AG Brand Doc. # 12272007-OKYD-PLKJ

DDR2 Fully Buffered

Memory Module

AETx61FBxx-[30D/25D]xxxX

512MB, 1GB, 2GB and 4GB

This Data Sheet describes AENEON DDR2 Fully Buffered DIMM on 240-pin modules with parity bit for address

and control bus and its main characteristics.

Key features

• Fully buffered DDR2 memory modules

• Available in single pack of densities 512MB/1GB/2GB/4GB

• Standard JEDEC pin configuration

• Validated by major motherboard vendors

• Fully RoHS compliant

• MBIST and IBIST test function

• Uses Advanced Memory Buffer [AMB] to effectively control and manages memory traffic

– Supports channel initialisation

– Supports the forwarding of southbound and northbound frames, servicing requests directed to a specific

AMB or DIMM, and merging the data in northbound frames

– Detects errors on the channel and reports them to the host memory controller

– Supports FB-DIMM configuration register set

– Acts as DRAM memory buffer for all operations

– Provides logic to support MEMBIST and IBIST design for test functions

• Module size of 133.35 x 30.35 x 8.2 (mm)

• Fully buffered DIMMs comes with heat sink

TABLE 1

Ordering Information

Product Type

1) Full Product Type / Sales Description

Module

Density

Organization Rank

Organization

Module Speed No of

Comp

Module Size

(mm)

DDR2-667, PC2-5300-555

AET661FB00-30DB19X 512MB 64M x 72 1Rx8 PC2-5300-555 8 133.35 x

30.35 x 8.2

AET761FB00-30DB19X 1GB 128M x 72 2Rx8 18

AET761FB28-30DB29X 1GB 128M x 72 2Rx4 18

AET861FB00-30DB19X 2GB 256M x 72 2Rx4 36

AET861FB28-30DC20X 2GB 256M x 72 2Rx8 18

AET961FB00-30DC10X 4GB 512M x 72 2Rx4 36

AET961FB48-30DC20X 4GB 512M x 72 4Rx8 36

DDR2-800, PC2-6400-555

AET861FB28-25DC20X 2GB 256M x 72 2Rx8 PC2-6400-555 18 133.35 x

30.35 x 8.2

AET961FB48-25DC20X 4GB 512M x 72 4Rx8 36

Summary of content (5 pages)

PAGE 1
DDR2 Fully Buffered Memory Module AETx61FBxx-[30D/25D]xxxX 512MB, 1GB, 2GB and 4GB This Data Sheet describes AENEON DDR2 Fully Buffered DIMM on 240-pin modules with parity bit for address and control bus and its main characteristics.
PAGE 2
DDR2 Fully Buffered Memory Module TABLE 2 Speed Grade Definition Speed Grade PC2 CAS-RCD-RP latencies Parameter –6400 –5300 5–5–5 5–5–5 Symbol Min. Max. Min. Max. Unit Note @ CL = 3 tCK 5 8 5 8 ns 1)2)3)4) @ CL = 4 tCK 3.75 8 3.75 8 ns 1)2)3)4) @ CL = 5 tCK 2.5 8 3 8 ns 1)2)3)4) @ CL = 6 tCK 2.5 8 — — ns 1)2)3)4) @ CL = 7 tCK 2.
PAGE 3
DDR2 Fully Buffered Memory Module Operating conditions This chapter describes the operating conditions. TABLE 3 DC Operating Conditions Parameter Symbol Limit Values Min. Unit Notes Nom. Max. 1.455 1.5 1.575 V 1) 1.425 1.5 1.590 V 2) VDD 1.7 1.8 1.9 V – Termination Voltage VTT 0.48 ×VDD 0.50 ×VDD 0.52 ×VDD V – EEPROM Supply Voltage VDDSPD 3.0 3.3 3.6 V – AMB Supply Voltage DC VCC AMB Supply Voltage DC + AC DRAM Supply Voltage DC Input Logic High(SPD) VIH(DC) 2.
PAGE 4
DDR2 Fully Buffered Memory Module Parameter Symbol Rating Min. Max. Unit Notes Voltage on VDDQ pin relative to VSS VDDQ –0.5 +2.3 V 2)3) Voltage on VDDL pin relative to VSS VDDL –0.5 +2.3 V 2)3) Voltage on any pin relative to VSS VIN, VOUT –0.3 +1.75 V 2) Voltage on VTT pin relative to VSS VTT –0.5 +2.3 V – °C 2)3) Storage Temperature TSTG –55 +100 1) Stresses greater than those listed under “Absolute Maximum Ratings“ may cause permanent damage to the device.
PAGE 5
DDR2 Fully Buffered Memory Module 5) Measured delay at FB-DIMM gold finger between the center of the 1st UI of a frame on the secondary northbound lane 0 (connector pins 142 & 143) and the center of the 1st UI of the same frame on the primary northbound lane 0 (connector pins 22 & 23).