Datasheet
BTS711L1
Semiconductor Group 7 2003-Oct-01
Truth Table
Channel 1 and 2 Chip 1
IN1 IN2 OUT1 OUT2 ST1/2 ST1/2
Channel 3 and 4
(equivalent to channel 1 and 2)
Chip 2
IN3 IN4 OUT3 OUT4 ST3/4 ST3/4
BTS 711L1 BTS 712N1
Normal operation
L
L
H
H
L
H
L
H
L
L
H
H
L
H
L
H
H
H
H
H
H
H
H
H
Open load Channel 1 (3) L
L
H
L
H
X
Z
Z
H
L
H
X
H(L
15)
)
H
L
L
H
H
Channel 2 (4) L
H
X
L
L
H
L
H
X
Z
Z
H
H(L
15)
)
H
L
L
H
H
Short circuit to V
bb
Channel 1 (3) L
L
H
L
H
X
H
H
H
L
H
X
L
16)
H
H(L
17)
)
L
16)
H
H
Channel 2 (4) L
H
X
L
L
H
L
H
X
H
H
H
L
16)
H
H(L
17)
)
L
16)
H
H
Overtemperature both channel L
X
H
L
H
X
L
L
L
L
L
L
H
L
L
H
L
L
Channel 1 (3) L
H
X
X
L
L
X
X
H
L
H
L
Channel 2 (4) X
X
L
H
X
X
L
L
H
L
H
L
Undervoltage/ Overvoltage X X L L H H
L = "Low" Level X = don't care Z = high impedance, potential depends on external circuit
H = "High" Level Status signal valid after the time delay shown in the timing diagrams
Parallel switching of channel 1 and 2 (also channel 3 and 4) is easily possible by connecting the inputs and
outputs in parallel (see truth table). If switching channel 1 to 4 in parallel, the status outputs ST1/2 and ST3/4
have to be configured as a 'Wired OR' function with a single pull-up resistor.
Terms
PROFET
IN2
ST1/2
OUT2
GND1/2
V
bb
V
OUT2
I
GND1/2
V
ON2
18
2
Leadframe
3
4
IN1
V
OUT1
V
ON1
I
L1
OUT1
5
17
V
IN1
V
IN2
V
ST1/2
I
bb
I
IN1
I
IN2
I
ST1/2
I
L2
R
GND1/2
V
bb
Chip 1
PROFET
IN4
ST3/4
OUT4
GND3/4
V
bb
V
OUT4
I
GND3/4
V
ON4
14
6
Leadframe
7
8
IN3
V
OUT3
V
ON3
I
L3
OUT3
9
13
V
IN3
V
IN4
V
ST3/4
I
IN3
I
IN4
I
ST3/4
I
L4
R
GND3/4
Chip 2
Leadframe (V
bb
) is connected to pin 1,10,11,12,15,16,19,20
External R
GND
optional; two resistors R
GND1/2
,R
GND3/4
= 150 Ω or a single resistor R
GND
= 75 Ω for
reverse battery protection up to the max. operating voltage.
15)
With additional external pull up resistor
16)
An external short of output to V
bb
in the off state causes an internal current from output to ground. If R
GND
is
used, an offset voltage at the GND and ST pins will occur and the V
ST low
signal may be errorious.
17)
Low resistance to V
bb
may be detected by no-load-detection