CompactPCI ® ICP-CM Intel® Celeron® M Low Power CPU Boards USER’S MANUAL Publication Number: PD00941013.
This user’s manual describes a product that, due to its nature, cannot describe a particular application. The content of this user’s manual is furnished for informational use only, is subject to change without notice, and should not be constructed as a commitment by Inova Computers GmbH. Inova Computers GmbH assumes no responsibility or liability for any errors or inaccuracies that may appear in this user’s manual.
Preface CompactPCI ® ICP-CM Preface Contents Unpacking and Special Handling Instructions ............................................... 6 Revision History ............................... 7 Three Year Limited Warranty .............. 8 1.0 ICP-CM CPU........................... 1-3 1.01 Interfacing ............................................................................................... 1.02 Peripherals ...............................................................................................
Preface ICP-CM 1.4 Hardware ............................. 1-11 1.41 Block Diagram........................................................................................ 1-11 Figure 1.41 Block Diagram ....................................................................................................... 1-11 1.42 Connector Location ............................................................................... 1-12 Figure 1.42 Connector Locations ..........................................................
Preface CompactPCI ® ICP-CM 2.7 Interrupt Configuration .......... 2-10 Table 2.70 CompactPCI Bus Interrupts ..................................................................................... 2-10 2.8 Timer / Counter ..................... 2-11 2.9 Watchdog ............................. 2-11 3.0 CompactPCI J1/J2 Connectors . 3-2 3.01 CompactPCI Connector Naming .............................................................. 3-2 Figure 3.01 Naming Convention as per PICMG 2.0 R3.0 Specification ........
Preface ICP-CM A2 ICP-HD-3(-ND) Interfaces ......... A-5 A2.1 COM1 & COM2 Interfaces ...................................................................... A-5 Figure A2.1 COM1 & COM2 Interface Pinout ............................................................................. A-5 Table A2.1 COM1 & COM2 Connector Signals ........................................................................... A-5 A2.2 Mouse & Keyboard Interfaces ..................................................................
Preface CompactPCI ® ICP-CM C1.9 USB Interface (USB 4) ............................................................................ C-11 Figure C1.9 USB Interface Pinout ............................................................................................. C-11 Table C1.9 USB Connector Signals ........................................................................................... C-11 C1.10 EIDE Interface ......................................................................................
Preface ICP-CM Unpacking and Special Handling Instructions This product has been designed for a long and fault-free life; nonetheless, its life expectancy can be severely reduced by improper treatment during unpacking and installation. Observe standard antistatic precautions when changing piggybacks, ROM devices, jumper settings etc.
Preface CompactPCI ® ICP-CM Revision History Revision History Manual MAN-ICP-CM Publication Number PD00941013.XXX Issue Brief Description of Changes PD00941013.001 Preliminary, First Release; All pages revised Doc. PD00941013.
Preface ICP-CM Three Year Limited Warranty Inova Computers (‘Inova’) grant the original purchaser of Inova products the following hardware warranty. No other warranties that may be granted or implied by anyone on behalf of Inova are valid unless the consumer has the expressed written consent of Inova. Inova warrants their own products (excluding software) to be free from defects in workmanship and materials for a period of 36 consecutive months from the date of purchase.
CompactPCI ® ICP-CM Product Overview 1 Product Overview Overview Contents 1.0 ICP-CM CPU........................... 1-3 1.01 Interfacing ............................................................................................... 1.02 Peripherals ............................................................................................... 1.03 Software .................................................................................................. 1.04 Graphics ..................................
Product Overview ICP-CM 1.4 Hardware ............................. 1-11 1.41 Block Diagram........................................................................................ 1-11 Figure 1.41 Block Diagram ....................................................................................................... 1-11 1.42 Connector Location ............................................................................... 1-12 Figure 1.42 Connector Locations .................................................
Product Overview CompactPCI ® ICP-CM 1.0 ICP-CM CPU Cutting edge technology makes the Inova Socket mPGA479M, Celeron® M single-board computer the ideal controller for a wide range of embedded (low power) industrial automation, military, medical, aerospace, imaging, telecommunications, process control and embedded/OEM applications.
Product Overview ICP-CM 1.01 Interfacing To satisfy today’s LAN-hungry industrial applications, Inova have implemented dual, independent 100BaseTx LAN Fast Ethernet interfaces as standard on the CPU’s front-panel - or fed to a rear I/O transition module on the backplane. Connectivity is further enhanced through the integration of the latest USB 2.
Product Overview CompactPCI ® ICP-CM 1.1 Specifications Processor 600MHz or 1.3GHz Socket mPGA479M mobile Intel Celeron M with 400MHz PSB, 512kByte L2 cache, passive or active cooling Memory Either 256MByte or 1GByte soldered 266MHz DDR SDRAM FLASH Socket For CompactFlash devices (Flash & MicroDrives) providing >4GByte mass-storage capacity A LAN Boot Phoenix BIOS Ver. 4.x Rel. 6.0 A ACPI 2.
Product Overview ICP-CM Fast Ethernet Additional 82551 controller PCI/PCI Universal bridge (Master or Slave) A Serialized interrupts A Universal (3.3/5.0V) V I/O support A 32-bit and Rear I/O On-Board I/O A Dual 10/100 Mbit/s Fast Ethernet A 1x front-panel 480Mbit/s, USB 2.0, (1x rear-panel 12Mbit/s, USB 1.1) A VGA (chipset or AGP) Rear I/O Standard to all CPU variants is option ‘D’: A VGA (chipset or AGP if installed) A Fast Ethernet ETH 1 (Intel 82551) A USB 1.
Product Overview CompactPCI ® ICP-CM 1.2 Functional Overview 1 Figure 1.20 ICP-CM Interfacing Inova’s CPUs have been prepared for rear I/O operation. Currently RIO-D is supported with VGA, single-channel Fast Ethernet, second EIDE channel, USB 1.1, mouse, keyboard, reset and loudspeaker (beeper) and a software selectable choice between LPT1, COM1& COM2 or floppy drive. Other rear I/O options may also be available (including customer specific) but are not referred to in this user’s handbook.
Product Overview ICP-CM Figure 1.21 ICP-CM Board Overview Socket mPGA479M for 600MHz or 1.3GHz Celeron M Processor 32-bit and rear I/O 256MB or 1GByte onboard DDR SDRAM IDE, USB 2.0, COM, PS-2, Floppy + LPT Interfaces CompactFlash Socket USB 2.0 Fast Ethernet Host Bridge Fast Ethernet AGP 4x Socket for Inova Graphic Module VGA, GigaST)R, TMDS ( DVI ) or TFT etc. Page 1-8 Reset Button & Hot-Swap LED ©2004 Inova Computers GmbH Doc. PD00941013.
Product Overview CompactPCI ® ICP-CM 1.3 Software 1 1.31 Windows XP (Professional / Embedded) Windows XP (Professional / Embedded) contains many new technologies and features designed for businesses of all sizes and for users who demand the most from their computers. It integrates the strengths of Windows 2000 (Professional), such as standards-based security, manageability and reliability, with Plug and Play convenience, simplified user interfacing, and innovative support services.
Product Overview ICP-CM 1.35 Windows CE Microsoft® Windows CE is an operating system designed for a wide variety of embedded systems and products, from hand-held PCs and consumer electronic devices to specialized industrial controllers and embedded communications devices.
Product Overview CompactPCI ® ICP-CM 1.4 Hardware 1 1.41 Block Diagram Figure 1.41 Block Diagram This block diagram is applicable to all Inova’s CM-based CPUs. Components and/or functionality may change without notice. Note 32-bit with or without Rear I/O (RIO) configurations are possible. User’s of NI peripheral cards should check to see whether signal conflict is possible with the RIO option selected. If in doubt, select the CPU version without RIO.
Product Overview ICP-CM 1.42 Connector Location Figure 1.42 Connector Locations 1.43 Connector Description Table 1.43 Connector Description Connector Description J1, J2 CompactPCI Interface Connector J4 AGP 4x for Optional Inova Graphic Piggyback J6 10BaseT/100BaseTx Fast Ethernet Interface ETH2 - [SiS 900 - chipset] J7 10BaseT/100BaseTx Fast Ethernet Interface ETH1 - [i82551] J9 CompactFlash Socket (MicroDrive or Flash) Page 1-12 ©2004 Inova Computers GmbH Doc. PD00941013.
Product Overview ICP-CM CompactPCI ® Table 1.43 Continued Connector J11 1 Description Internal USB (1.1) interface for additional USB devices (USB 5) J12, J13, J14 Hard Disk module, Mouse, Keyboard, COM, FD, USB 2.0 and LPT1 interfaces J15 External USB 2.0 interface (USB 1) J17 VGA interface (soldered D-Sub for onboard Chipset or from AGP piggyback) SW1 Reset button switch 1.44 Front-Panel Features Table 1.
Product Overview ICP-CM Figure 1.44 Front-Panel Options The front-panels shown in Figure 1.44 show the tremendous flexibility built into Inova’s CPU concept. From left, the standard CPU is 4TE with dual Fast Ethernet, USB (2.0) and VGA graphic connections. If, instead of VGA graphics, PanelLink or GigaST)R is required then an AGP piggyback is installed on J4 for this purpose.
Product Overview CompactPCI ® ICP-CM 1.45 Interface Positions 1 Figure 1.45 Interfaces Figure 1.45 shows the typical positioning of the front panel extension modules for mouse, keyboard, COM1, COM2, and LPT interfaces. Note A hard disk, if installed, will generally be fitted to the piggyback containing the combined PS-2 mouse / keyboard, USB2.0, COM1 and COM2 interfaces. Doc. PD00941013.
Product Overview ICP-CM 1.46 Construction - 4HP Standard CPU This standard CPU configuration comprises:N Passively cooled base with chipset VGA graphics, dual Fast Ethernet and single USB 2.0 interface for mouse, keyboard, FD, CD-ROM etc. The minimum airflow requirements must be compatible with the selected ‘processor speed, CPU damage could result otherwise ! Figure 1.46 Construction of CPU with Heat-Sink Assembly F G D D G D E D D E E D E H G H G Page 1-16 ©2004 Inova Computers GmbH Doc.
CompactPCI ® ICP-CM Product Overview 1.47 Construction - 8HP Standard CPU This standard CPU configuration comprises:N Passively cooled base with chipset VGA graphics, dual Fast Ethernet, three USB 2.0 interfaces, combined PS-2 mouse / keyboard, COM1 and COM2 interfaces. Behind the extended front-panel is a platform for any IDE HD or Flash device with additional interfacing for FD and LPT - refer to Appendix A for further information.
Product Overview ICP-CM 1.48 Construction - 8HP Standard CPU with AGP This standard CPU configuration comprises:N Passively cooled base with AGP 4x Radeon R7000-based graphics, dual Fast Ethernet, three USB 2.0 interfaces, combined PS-2 mouse / keyboard, COM1 and COM2 interfaces. Behind the extended front-panel is a platform for any IDE HD or Flash device with additional interfacing for FD and LPT - refer to Appendix A for further information.
Product Overview CompactPCI ® ICP-CM 1.49 Power Requirements This CPU board is a high-performance, low-power device and, as such, requires voltage, current and power timing as defined in table 1.49 for correct operation. The Inova >70W PSUs fulfil these requirements and reference should be made to this products’ data sheet and user’s manual. Table 1.49 ICP-CM Power Reqirements Supply Voltages Signal Voltage +5V 5.0V +5%/-3% +3.3V 3.3V +5%/-3% 1.8A V I/O 5.0V +5%/-3% or 3.3V +5%/-3% 0.
Product Overview ICP-CM 1.50 Power Consumption The illustration provided in figure 1.50 is for reference only and serves to show the ‘typical-maximum’ power consumption of the ICP-CM CPU. Variations in ‘processor manufacture and onboard silicon make accurate testing impossible and hence, the figures shown in this illustration are subject to fluctuation. Note: There is no such thing as a typical application and so, the CPU power consumption was measured with the ‘processor in idle state, in BIOS mode (i.
Product Overview CompactPCI ® ICP-CM 1.51 Thermal Considerations Being a passively-cooled design, a purpose-built, thermally optimized heat-sink is all that removes the heat from the CPU. The effective surface area of the radiator unit mounted on the single slot (4HP) CPU version is less that of the 8HP CPU and therefore, necessitates more airflow (or air circulation) to keep it cool. As a guideline, the figures published in table 1.51 show the minimum airflow required to maintain stable operation.
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CompactPCI ® ICP-CM Configuration Configuration 2 Configuration Contents 2.0 Memory Map........................... 2-2 Figure 2.00 System Architecture ................................................................................................. 2-2 2.1 I/O Mapped Peripherals............. 2-4 Table 2.10 Legacy I/O Map (ISA Compatible) ............................................................................ 2-4 Table 2.10 Legacy I/O Map (ISA Compatible) Contd. ....................................
Configuration ICP-CM 2.0 Memory Map Figure 2.00 System Architecture Page 2-2 ©2004 Inova Computers GmbH Doc. PD00941013.
Configuration CompactPCI ® ICP-CM 2 Note: 96kBytes are reserved for option ROM space: - USB Legacy (32kByte) - Ethernet Boot (16kByte) - PXE Boot (48kByte) In addition, 3rd party devices can also have their ‘space’ here such as additional networking cards, SCSI or FireWire etc. The total available space cannot exceed 96kByte. Doc. PD00941013.
Configuration ICP-CM 2.1 I/O Mapped Peripherals The original PC-XT and PC-AT desktop computer (ISA bus) specification allows for 10-bit I/O addressed peripherals. This permits peripheral boards to be I/O mapped from 0h to 3FFh. CompactPCI systems permit the full 16-bit addressing capability of the Intel 80x86 ‘processors, from 0h to 0FFFFh.
Configuration CompactPCI ® ICP-CM Table 2.10 Legacy I/O Map (ISA Compatible) Contd.
Configuration ICP-CM 2.2 Memory Mapped Peripherals PC-AT desktop computers (ISA bus) allow 24-bit memory addressed peripherals. This decoding permits peripheral boards to be mapped in the Intel 80x86 memory map from 0h to 0FFFFFFh. Inova’s CompactPCI systems allow the full 32-bit addressing capability of the Intel Pentium 4 range of ‘processors so that memory mapped peripheral devices may be mapped locally to the ‘processor board at any location in the memory map not being used by other devices (e.g.
Configuration CompactPCI ® ICP-CM Table 2.
Configuration ICP-CM 2.5 Inova CM SMB Devices Table 2.50 shows the addressing of the SMB (System Management Bus) Devices Table 2.50 SMB Devices Address b[7:1] Page 2-8 Device 0101 100 LM87 (Temperature Monitor) 1010 000 EEPROM SPD DDR Bank 0 1010 101 EEPROM TOP EXTENSION (e.g. ICP-HD-3) ID 1010 110 EEPROM RIO PANEL ID 1010 111 EEPROM Vital Product Data / General Purpose 1101 001 ICS952001 (Timing Hub) ©2004 Inova Computers GmbH Doc. PD00941013.
Configuration CompactPCI ® ICP-CM 2.6 Inova CM PCI Device List Table 2.60 shows the available PCI devices both on-board and off-board (CompactPCI backplane). It should be noted that the interrupt routing assumes a standard Inova backplane configuration with a right-hand system slot. 2 Table 2.60 Legacy I/O Map (ISA Compatible) Bus No.
Configuration ICP-CM 2.7 Interrupt Configuration The CompactPCI specification defines a total of six interrupt signals on the backplane. INTA# through INTD# are used to route interrupts from the CompactPCI boards to the PIC on the ‘processor board. The interrupt request level generated by the device depends on the backplane slot number which the board is plugged into, and the interrupt signal which is driven by the particular PCI device.
Configuration CompactPCI ® ICP-CM 2.8 Timer / Counter The IBM-compatible architecture configures the programmable timer / counter (Intel 8254-compatible) devices for system-specific functions as shown in Table 2.80. The BIOS programs Timer 0 to generate an interrupt approximately every 55ms (18.2 times per second.) This interrupt, known as the system timer tick, updates the BIOS clock and turns off the floppy disk motor drive after a few seconds of inactivity for example.
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Interfaces CompactPCI ® ICP-CM Interfaces Interfaces Contents 3.0 CompactPCI J1/J2 Connectors . 3-2 3.01 CompactPCI Connector Naming .............................................................. 3-2 Figure 3.01 Naming Convention as per PICMG 2.0 R3.0 Specification ........................................ 3-2 3.02 CompactPCI J1 Connector ....................................................................... 3-2 Figure 3.02 J1- 32-Bit CompactPCI Bus Interface Connector .................................
Interfaces ICP-CM 3.0 CompactPCI J1/J2 Connectors The CompactPCI standard is electrically identical to the PCI local bus standard but has been enhanced to support rugged industrial environments and up to 8 slots. The standard is based upon a 3U board size and uses a rugged pin-in-socket hard 2mm connector (IEC-1076-4-101.) 3.01 CompactPCI Connector Naming Figure 3.01 Naming Convention as per PICMG 2.0 R3.0 Specification 3.02 CompactPCI J1 Connector Figure 3.
Interfaces Table 3.03 32-Bit CompactPCI J1 Pin Assignment CompactPCI ® ICP-CM Pin Nr Row A Row B Row C Row D Row E J1-25 +5V REQ64# ENUM# +3.3V +5V J1-24 AD[1] +5V V( I / O ) AD[0] ACK64# J1-23 +3.3V AD[4] AD[3] +5V AD[2] J1-22 AD[7] GND +3.3V AD[6] AD[5] J1-21 +3.3V AD[9] AD[8] M66EN C / BE[0]# J1-20 AD[12] GND V( I / O ) AD[11] AD[10] J1-19 +3.3V AD[15] AD[14] GND AD[13] J1-18 SERR# GND +3.3V PAR C / BE[1]# J1-17 +3.
Interfaces ICP-CM Table 3.04 32-Bit CompactPCI J2 Pin Assignment (Std.
Interfaces CompactPCI ® ICP-CM Table 3.04 32-Bit CompactPCI J2 Pin Assignment (Std. - with Rear I/O (D)) - Contd.
Interfaces ICP-CM Option RIO(C1) RIO(D) No Yes Intel 82551 Intel 82551 Yes Yes Keyboard Only Yes 2nd IDE Channel Yes Yes Reset & Beeper Yes Yes LPT1 Software Selectable Software Selectable COM1 & COM2 Software Selectable Software Selectable Floppy Disk (A or B) Software Selectable Software Selectable VGA Fast Ethernet USB 1.1 PS-2 Mouse & Keyboard One of Table 3.
Interfaces CompactPCI ® ICP-CM 3.1 CompactPCI Backplane The form factor defined for CompactPCI boards is based upon the Eurocard industry standard. Both 3U (100 mm by 160 mm) and 6U (233 mm by 100 mm) board sizes are defined. A CompactPCI system is composed of up to eight CompactPCI cards. The CompactPCI backplane consists of one System Slot, and up to seven Peripheral Slots. The System Slot provides arbitration, clock distribution, and reset functions for all boards on the bus.
Interfaces ICP-CM Figure 3.10 Inova’s 32-Bit CompactPCI 8-Slot Backplane - RH System Slot Note: The logical slots are different to the physical slots. The slot marked with the ‘g‘ is the System Slot and always assigned logical ‘1’. The neighbouring slot is logical ‘2’! Page 3-8 ©2004 Inova Computers GmbH Doc. PD00941013.
Interfaces CompactPCI ® ICP-CM 3.2 Interfaces 3.21 J6 & J7 Ethernet J6 is a Fast Ethernet interface from the SiS chipset while J7 [ETH1] is an additional Fast Ethernet from the dedicated on-board controller. Both RJ45 interfaces are available as standard on the CPU front-panel and provide support for 10BaseT and 100BaseTX twisted pair standards. Figure 3.
Interfaces ICP-CM 3.22 J17 VGA Interface J17 is available on the CPU front-panel if this option is required and if this position is not already occupied by an AGP piggyback for PanelLink (TFT) or GigaST)R communication. The 15-pin high-density D-Sub connector forms the physical interface for the video on the ICP-CM which is integrated within the chipset. The amount of graphic memory allocated to the chipset video option is defined in BIOS.
Interfaces Figure 3.23 High-Density D-Sub VGA Interface Pinout 5 1 6 15 11 Table 3.23b Video Output Connector Signals Pin No. 3 Signal 1 Analog RED 2 Analog GREEN 3 Analog BLUE 4 N/C CRT Ground 9 +5V (DDC) 10 CRT Ground 11 N/C 12 DDC-SDA 13 HSYNC 14 VSYNC 15 DDC-SCL Refresh Rates (Hz) 5, 6, 7, 8 Refresh Rates (Hz) 10 Refresh Rates (Hz) CompactPCI ® ICP-CM Doc. PD00941013.
Interfaces ICP-CM 3.24 J19 USB Interface J19 is located as standard on the front panel. All standard USB 2.0 and 1.1 compatible devices can be connected to this interface. Figure 3.24 USB Interface Pinout 1 2 3 4 Table 3.24 USB Connector Signals Pin No. Page 3-12 Signal 1 +5V 2 USB P0- 3 USB P0+ 4 GND ©2004 Inova Computers GmbH Doc. PD00941013.
Interfaces CompactPCI ® ICP-CM 3.25 J10 Hot-Swap Interface This PCB-level interface is used for the front-panel integrated micro-switch and blue LED in accordance with the PICMG 2.1 R2.0 specifications. 3.26 SW1 Reset Button The reset button allows the CPU to be reset in the event that it ‘hangs’ Performing a reset in this manner is known as a ‘warm’ start as power is not removed from the peripherals (IDE etc.) 3.
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ICP-HD-3 CompactPCI ® Appendix A ICP-HD-3 ICP-HD-3 Contents A1 ICP-HD-3(-ND) CPU Extension .. A-2 A1.1 ICP-HD-3(-ND) Front-Panels (8HP or 12HP) ............................................. A-2 Figure A1.1 ICP-HD-3(-ND) CPU Front-Panels ............................................................................ A-2 A1.2 IDE Carrier Board ICP-HD-3(-ND) ............................................................. A-3 Figure A1.2 Interface Location of the ICP-HD-3(-ND) Module .........................
ICP-HD-3 Appendix A A1 ICP-HD-3(-ND) CPU Extension Combined PS-2 mouse / keyboard, USB (2.0), COM ports, LPT, mass storage and slim-line FD interfaces are supplied on the ICP-HD-3(-ND) - a CPU add-on board. Two versions exist - one is supplied with a hard disk and one without. Both versions are functionally identical.
ICP-HD-3 CompactPCI ® Appendix A A1.2 IDE Carrier Board ICP-HD-3(-ND) Figure A1.2 illustrates the construction of the integrated ICP-HD-3 carrier board and the location of the interface connectors. Table A1.2 gives a description of these interfaces. Care should be exercised when attaching the LPT interface to this carrier board. Here the connection is via a length of flex cable between J11 of the carrier and J13 on the LPT module.
ICP-HD-3 Appendix A Table A1.2 Interface Description of the ICP-HD-3(-ND) Module Connector J1 J2 Description Open: COM1 is configured for RS232 communication Closed: COM1 is configured for RS485 communication Open: COM2 is configured for RS232 communication Closed: COM2 is configured for RS485 communication J3 COM2 physical interface J4 Reset - shorting these pins causes the CPU to reset J5 PS-2 mouse & keyboard physical interface J6 USB 2.
ICP-HD-3 CompactPCI ® Appendix A A2 ICP-HD-3(-ND) Interfaces The carrier board serves not just to mount an IDE mass-storage device - it also provides the user with a wealth of familiar standard PC interfaces. A2.1 COM1 & COM2 Interfaces The two COM ports feature a complete set of handshaking and modem control signals, maskable interrupt generation and highspeed data transfer rates.
ICP-HD-3 Appendix A A2.2 Mouse & Keyboard Interfaces The physical PS-2 mouse & keyboard interface is brought out on this 8HP front-panel. Connector pinout and description are provided in Figure A2.2 and Table A2.2 respectively. Note: If the mouse and keyboard ports are used in rear I/O applications then they should not be used from the frontpanel. Communicating from both mouse and keyboard sources is physically possible but is not recommended! Figure A2.
ICP-HD-3 CompactPCI ® Appendix A A2.3 USB 2.0 Interfaces Standard to all ICP-HD-3 carrier board modules are the two USB (2.0) interfaces which are backward compatible to USB 1.1 devices. Figure A2.3 USB Interface Pinout 1 2 3 4 Table A2.3 USB Connector Signals Pin No.
ICP-HD-3 Appendix A A2.4 EIDE Interface Standard to all ICP-HD-3 carrier board modules is the 3.5” EIDE hard-disk header. This has a standard (commercial PC) pinout and requires no further mention here. Note: To conform with the UDMA 66 (or higher) standards, only suitable, commercially available 80-strand ribbon cable should be used. Failure to do so may result in data transmission errors or even cause the CPU to crash! A2.
IPB-FPE12 CompactPCI ® Appendix B IPB-FPE12 IPB-FPE12 Contents B1 IPB-FPE12 CPU Extension ........ B-2 B1.1 J13 Interface for LPT1 ............................................................................... B-2 B1.2 IPB-FPE12 Front-Panel (4HP or 12HP) ....................................................... B-2 Figure B1.2 IPB-FPE12 Stand-Alone or Integrated with CPU ........................................................ B-2 B1.3 LPT1 Piggyback .....................................................
IPB-FPE12 Appendix B B1 IPB-FPE12 CPU Extension The Inova IPB-FPE12 adds LPT functionality to any Inova Pentium M, Celeron M or Pentium 4(M) CPU. The piggyback is available as a stand-alone device with its own 4HP front-panel or integrated within a 12HP front-panel. The information documented here is valid regardless of the connection choice. B1.1 J13 Interface for LPT1 The control of the LPT interface is performed through the J11 connector on the CPU’s hard-disk carrier board.
IPB-FPE12 CompactPCI ® Appendix B B1.3 LPT1 Piggyback Figure B1.3 illustrates the construction of the stand-alone IPB-FPE12 piggyback and the upperside location of the J13 connector. The same mechanical construction applies to the integrated version. Care should be taken to ensure that pin 1 of J13 on the CPU base board is linked by an appropriate length of flex cable to pin 1 on the ICP-HD-3 piggyback.
IPB-FPE12 Appendix B Table B1.3 IPB-FPE12 Connector Description Connector J13 Description LPT1 B1.4 LPT1 Interface The physical LPT1 interface is either integrated into a 12HP CPU front-panel or available as a separate 4HP unit. The piggyback located behind this interface connects to the hard-disk carrier board (ICP-HD-3) mounted J13 connector. Figure B1.4 LPT1 Interface Pinout 13 1 25 14 Table B1.4 LPT1 Connector Signals Pin No. Page B-4 Signal Pin No.
ITM-RIO CompactPCI ® Appendix C ITM-RIO ITM-RIO Contents C1 ITM-RIO CPU Extension ............ C-2 C1.1 ITM-RIO-D Configurations ....................................................................... C-2 Table C1.10 Valid Rear I/O Configurations ................................................................................. C-2 Table C1.11 Rear I/O Module Functionality ................................................................................ C-2 C1.2 ITM-RIO Rear-Panels (4HP or 8HP) .........
ITM-RIO Appendix C C1 ITM-RIO CPU Extension The Inova Pentium 4(M), Pentium M or Celeron M CPUs are more than just a computing platform - they are a complete, well thought-out concept. Nowhere is this more apparent than in the colourful rear I/O selection. With a choice of three full-length (80mm) plug-in modules conforming to the latest Inova rear I/O (D) specification and the rear I/O (C1) options, the major industrial requirements have been satisfied. C1.
ITM-RIO CompactPCI ® Appendix C C1.2 ITM-RIO Rear-Panels (4HP or 8HP) As with front-panel I/O, the physical interfaces from the ITM-RIO-D-x rear I/O module are brought out to a face plate (rear panel). Figure C1.2 illustrates the three standard formats available (at time of press.) Figure C1.2 The rear Panels of the Inova ITM-RIO-D-x C The rear I/O options described here do not detract from the latest PICMG 2.0 R3.0 specification. The VGA option in table C1.
ITM-RIO Appendix C C1.3 ITM-RIO-D-x Transition Module Figure C1.3 illustrates the construction of the ITM-RIO-D-x module. The connections are straight forward and need little by way of explanation. None of the connectors can be incorrectly inserted thanks to the mechanical keying of both plug and socket. Table C1.3 explains the significance of the interfaces labelled in Figure C1.3. Note: Care should be exercised when inserting the cables linking the COM, LPT, EIDE and floppy etc.
ITM-RIO Appendix C CompactPCI ® Table C1.3 ITM-RIO-D-x Connector Description Connector Description J1 CompactPCI rear I/O connector J2 Standard 3.
ITM-RIO Appendix C C1.4 COM1 & COM2 Interfaces The two COM ports feature a complete set of handshaking and modem control signals, maskable interrupt generation and highspeed data transfer rates. An 8HP rear-panel (Figure C1.2) brings out the physical COM1 & COM2 interfaces. Note: If the COM ports are used in rear I/O applications then they should not be used from the CPU front-panel. The front panel COM port connections are disabled automatically if using the rear I/O COM port option. Figure C1.
ITM-RIO CompactPCI ® Appendix C C1.5 LPT1 Interface The physical LPT1 interface of the rear I/O panel illustrated in Figure C1.2 connects to J9 on the baseboard for. Note: If the LPT port is used in rear I/O applications then it should not be used from the front-panel. Communicating from both sources is physically possible but is not recommended! Figure C1.5 LPT1 Interface Pinout 13 1 25 14 Table C1.5 LPT1 Connector Signals Pin No. Signal Pin No.
ITM-RIO Appendix C C1.6 Mouse & Keyboard Interfaces The physical PS-2 keyboard interface is brought out on either a 4HP or 8HP rear -panel, the mouse interface is only available on the 8HP version (Figure C1.2) Connector pinout and description are provided in Figure C1.6 and Table C1.6 respectively. Note: If the mouse, keyboard ports are used in rear I/O applications then they should not be used from the frontpanel.
ITM-RIO CompactPCI ® Appendix C C1.7 VGA Interface The VGA signals appearing on this interface are from the CPU chipset or AGP piggyback (if configured for rear I/O signalling). Figure C1.7 and Table C1.7 provide the pinout and signal description of this standard VGA interface respectively. With an AGP video piggyback installed, the video image appearing on this rear I/O interface can be selected to be different to that appearing on the front-panel.
ITM-RIO Appendix C C1.8 Fast Ethernet Interface Standard to all rear I/O (D) transition modules is the Fast Ethernet connection. Figure C1.8 and Table C1.8 provide the pinout and signal description of this standard Ethernet interface respectively. Although the LEDs feature on the Ethernet connector, these are not physically connected to the rear I/O interface board.
ITM-RIO CompactPCI ® Appendix C C1.9 USB Interface (USB 4) Standard to all rear I/O (D) transition modules is the peripheral USB (1.1) port. Figure C1.9 and Table C1.9 provide the pinout and signal description of this standard Ethernet interface respectively. Figure C1.9 USB Interface Pinout 1 2 3 4 Table C1.9 USB Connector Signals Pin No.
ITM-RIO Appendix C C1.10 EIDE Interface Standard to all rear I/O transition modules is the 3.5” EIDE hard-disk header. This has a standard (commercial PC) pinout and requires no further mention here. Note: To conform with the ATA 5 standard, only suitable, commercially available 80-strand ribbon cable should be used. Failure to do so may result in data transmission errors or even cause the CPU to crash! C1.
ITM-RIO CompactPCI ® Appendix C C1.12 ITM-RIO(C&D)-FHLU Extension To further enhance the I/O and serviceability of their CPUs, Inova have introduced a rear I/O module (figure C1.12) that connects to a CompactPCI connector on the rear of the Master Slot on the backplane. All standard Inova backplanes are equipped with this R2 connector so that even if the rear I/O functionality is not requested at time of order, it can be implemented at a later stage.
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IPM-ATA CompactPCI ® Appendix D IPM-ATA IPM-ATA D1 IPM-ATA CPU Extension .......... D-2 D1.1 rJ2 Interface ............................................................................................ D-2 Figure D1.1a Dedicated IPM-ATA Backplane ............................................................................... D-2 D1.1 rJ2 Interfaces (Contd.) ............................................................................ D-3 Figure D1.1b The Complete Connection Picture .....................
IPM-ATA Appendix D D1 IPM-ATA CPU Extension Inova Plug-In Module (IPM-) offers the user the ability to exchange a hard-disk for example without having to remove the CPU from the CompactPCI enclosure and then dismantle it etc. Currently, three units exist that provide industry with hard-disk, Compact FLASH, MicroDrive or ATA PCMCIA format mass storage capability. D1.
IPM-ATA CompactPCI ® Appendix D D1.1 rJ2 Interfaces (Contd.) Standard 80-pin IDE ribbon-cable is used to connect rJ2 of the ITM-RIO modules to the IPM’s dedicated backplane. The use of ribbon cable permits the mass-storage device(s) to be positioned at any convenient location within the CompactPCI enclosure. Figure D1.1b shows the complete configuration (CompactPCI to IPM-XXX) Figure D1.1b The Complete Connection Picture KEY: 1. IPM-ATA carrier board 2.
IPM-ATA Appendix D D1.2 IPM-ATA-HD The IPM-ATA-HD has provision for one standard notebook (2.5”) EIDE device (FLASH or hard-disk) and one Compact FLASH or MicroDrive site. Figure D1.2 illustrates the significant connectors for this device while Table D1.2 indicates the jumper positions for the various Master/Slave device configurations. Figure D1.2 IPM-ATA-HD Board Layout 1 2 3 Note: The hard disk is jumpered seperately for Master / Slave operation Table D1.
IPM-ATA CompactPCI ® Appendix D D1.3 IPM-ATA-CF The IPM-ATA-CF has provision for one or two standard Compact FLASH or MicroDrive devices. Figure D1.3 illustrates the significant connectors for this device while Table D1.3 indicates the jumper settings for the various Master/Slave device configurations. Figure D1.3 IPM-ATA-CF Board Layout 1 2 3 Table D1.
IPM-ATA Appendix D D1.4 IPM-ATA-PCMCIA The IPM-ATA-PCMCIA has provision for one standard ATA PCMCIA device and one Compact FLASH or MicroDrive site. Figure D1.4 illustrates the significant connectors for this device while Table D1.4 indicates the jumper settings for the various Master/Slave device configurations. Figure D1.4 IPM-ATA-PCMCIA Board Layout 1 2 3 Table D1.
IPM-ATA CompactPCI ® Appendix D D1.5 Device Compatibility Because of the diversity of Compact FLASH devices available with different architectures and error recovery routines etc. there is a strong possibility that some Master / Slave combinations will fail to be recognised by the BIOS. To help highlight the problem, Inova have provided the test report shown in Table D1.5 which should be regarded as a guide when choosing to pick-and-mix devices.
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AGP-R7000 CompactPCI ® Appendix E AGP-R7000 AGP-R7000 E1 AGP-R7000 CPU Extension....... E-2 Table E1.00 AGP Piggyback Configurations ................................................................................. E-2 E1.1 Specifications ........................................................................................... E-3 E1.2 J4 Interface ............................................................................................... E-4 Figure E1.
AGP-R7000 Appendix E E1 AGP-R7000 CPU Extension The AGP-R7000 is an Inova AGP 4x ATI Radeon-based graphic extension for use with the ICP-P4, ICP-P4(M), ICP-PM and ICP-CM CPUs. By utilizing the power of the ATI Radeon 7000 equipped with 32MByte of SDRAM, a graphic performance improvement of some 50%1.) can be expected when compared to the on board (chipset) solution.
AGP-R7000 CompactPCI ® Appendix E E1.
AGP-R7000 Appendix E E1.2 J4 Interface Communication to and from the host CPU is through J4 (refer to figure E1.20) - the AGP interface. The video output, as discussed earlier, is hardware configured (at time of purchase) for different front and rear panel modes - refer to table E1.00. The TFT option (J3/J5) is always present. The J4 AGP interface on the graphic piggyback is electrically identical to AGP, but has a smaller form factor and uses a different connector. Table E1.
AGP-R7000 CompactPCI ® Appendix E Table E1.20 J4 Pinout Pin No. Signal Pin No. Signal 1 USB6+ 2 GND 3 PC_BEEP 4 USB6- 5 VCC3.3 6 AC_RESET# 7 SYNC 8 BITCLK 9 SDATA_OUT 10 VCC5 11 INTB# 12 SDATA_IN 13 GND 14 INTA# 15 CLK 16 RST# 17 REQ# 18 GND 19 ST0 20 GNT# 21 VCC3.3 22 ST1 23 ST2 24 - 25 RBF# 26 VCC3.3 27 - 28 PIPE# 29 GND 30 WBF# 31 SBA0 32 SBA1 33 SBA2 34 GND 35 SB_STB 36 SBA3 37 VCC3.
AGP-R7000 Appendix E Table E1.20 J4 Pinout - Contd. Pin No. Page E-6 Signal Pin No. Signal 61 GND 62 AD22 63 AD19 64 AD20 65 AD17 66 GND 67 C/BE2# 68 AD18 69 VDDQ1.5 70 AD16 71 IRDY# 72 FRAME# 73 DEVSEL# 74 VDDQ1.5 75 - 76 TRDY# 77 GND 78 STOP# 79 PERR# 80 PME# 81 SERR# 82 GND 83 C/BE1# 84 PAR 85 VDDQ1.5 86 AD15 87 AD14 88 AD13 89 AD12 90 VDDQ1.
AGP-R7000 CompactPCI ® Appendix E E1.3 J3 & J5 IBP-GS-MULTILINK (TFT) Interfaces To address an almost unlimited number of cascaded digitally connected (GigaST)R) TFT displays with optional CAN control and PanelLink Slave connectivity, the Inova GigaST)R transmitter piggyback, IPB-GS-MULTILINK needs to be installed adjacent to the AGP piggyback. This connection is made through connectors J3 and J5 on the upper side of the piggyback as shown in figure E1.30. Table E1.
AGP-R7000 Appendix E Table E1.30 J3 & J5 Interface Pinout J3 Connector Pin No. Signal J5 Connector Pin No.
AGP-R7000 CompactPCI ® Appendix E E1.4 J1 Front-Panel VGA/TMDS Interface Standard analog VGA or digital (PanelLink) monitors can be connected to the AGP-R7000 via the 15-pin, D-Sub J1 interface. A bank of DIP switches (J2) enables the resolution of connected TFT or TMDS displays to be set or permits the system software to access the DDC data from standard analog or digital TMDS devices and set the resolution automatically. Figure E1.
AGP-R7000 Appendix E Table E1.41 J2 DIP Switch Settings - Digital TMDS (PanelLink) or DVI-D SW3 SW2 SW1 Resolution Comments OFF OFF OFF Disabled See Note Below OFF OFF ON 640 x 480 60Hz OFF ON OFF 800 x 600 60Hz OFF ON ON 1024 x 768 60Hz ON OFF OFF 1280 x 1024 60Hz ON OFF ON Reserved ON ON OFF Reserved ON ON ON Reserved Table E1.
AGP-R7000 CompactPCI ® Appendix E Note: If the AGP piggyback is installed, the VGA connector associated with the chipset graphic must be removed. For this reason, the AGP piggyback is NOT available as an accessory to be added as an after thought! E1.5 Rear I/O VGA Interface Refer to the rear I/O documentation for video interfacing connectivity.
