Features: Standard ATA/IDE Bus Interface - 512 Bytes / Sector - ATA command set compatible - Selectable Master/Slave Setting Capacities - Integral Z Series (MLC) 16GB, 32GB, 64GB - Integral E Series (SLC) 16GB Data Transfer mode - Support Data Transfer up to PIO mode 6 - Support Data Transfer up to Multiword DMA mode 2 - Support Data Transfer up to Ultra DMA mode 5 Performance Integral Z Series (MLC Flash) Sustain Read Speed up to 35MB/s Sustain Write Speed up to 15MB/s
TABLE OF CONTENTS 1.0 BLOCK DIAGRAM .................................................................................................................... 4 1.1 CAPACITY SPECIFICATION .................................................................................................... 4 2.0 SPECIFICATION ........................................................................................................................ 5 2.1 PIN ASSIGNMENTS................................................................
1.0 Block Diagram 1.
2.0 Specification 2.
29 GND 30 nDMACK 31 NC 32 DMARQ 33 NC 34 GND 35 GND 36 NC 37 HA0 38 NC 39 HA1 40 GND 41 HA2 42 IORDY 43 nIOIS16 44 INTRQ 45 nPDIAG 46 nHCS0 47 3V3 48 nHCS1 49 3V3 50 GND 51 3V3 52 nDASP 2.2 Pin Description Pin No. Signal I/O* Description 22 -RESET I Hardware reset signal from the host 1, 3, 5, 7, 11, 13, 17, HD0~HD15(Device Data) I/O 16-bit bi-direction Data Bus. DD(7:0) are 19, 20, 16, 14, 12, used for 8-bit register transfers.
DSTROBE(UDMA data When UDMA mode DMA Read is active, strobe) this signal is the data-in strobe generated by the device. 26 CSEL(Cable select) I This pin is used to configure this device as Device 0 or Device 1. 30 -DMACK(DMA I This signal is used by the host in respond acknowledge) 44 INTRQ(Interrupt) to DMARQ to initiate DMA transfer.
“O” An output from the device to the host system. “I/O” An input/output(bi-direction) common. “P” Power supply. 3.0 Electrical Characteristics 3.1 Absolute Maximum Rating Item Symbol Parameter MIN MAX Unit 1 VDD-VSS DC Power Supply -0.3 +5.5 V 2 VIN Input Voltage Vss-0.3 VDD+0.3 V 3 Ta Operating Temperature 0 +70 0 -25 +85 0 4 Tst Storage Temperature C C Parameter Symbol MIN TYP MAX Unit VDD Voltage VDD 3.0 3.3 3.6 V 4.5 5.0 5.5 V 3.
3.3 AC Characteristics 3.3.
PIO timing parameters t0 Cycle time t1 Address valid to (min) DIOR-/DIOW- setup (min) t2 DIOR-/DIOW- (min) t2i DIOR-/DIOW- recovery time Mode 0 Mode 1 Mode2 Mode 3 Mode 4 Note ns ns ns ns ns 600 383 240 180 120 70 50 30 30 25 165 125 100 80 70 1 -- -- -- 70 25 1 1,4 (min) t3 DIOW- data setup (min) 60 45 30 30 20 t4 DIOW- data hold (min) 30 20 15 10 10 t5 DIOR- data setup (min) 50 35 20 20 20 t6 DIOR- data hold (min) 5 5 5 5 5 t6z
negated at the time tA after the activation of DIOR- or DIOW-, then tRD shall be met and t5 is not applicable. 4. Mode may be selected at the highest mode for the device if CS(1:0) and DA(2:0) do not change between read or write cycle or selects at the highest mode supported by the slowest device if CS(1:0) and DA(2:0) do change between read or write cycles.
3.3.
(Device terminating a Multiword DMA data burst) (Host terminating a Multiword DMA data burst) 13
Multiword DMA timing parameters Mode 0 Mode 1 Mode2 ns ns ns Note t0 Cycle time (min) 480 150 120 See note tD DIOR-/DIOW- asserted pulse width (min) 215 80 70 See note tE DIOR- data access (max) 150 60 50 tF DIOR- data hold (min) 5 5 5 tG DIOR-/DIOW- data setup (min) 100 30 20 tH DIOW- data hold (min) 20 15 10 tI DMACK to DIOR-/DIOW- setup (min) 0 0 0 tJ DIOR-/DIOW- to DMACK hold (min) 20 5 5 tKR DIOR- negated pulse width (min) 50 50 25 See not
3.3.
Ultra DMA data burst timing descriptions 16
(Initialing an Ultra DMA data-in burst) (Sustained Ultra DMA data-in burst) 17
(Device terminating an Ultra DMA data-in burst) (Host terminating an Ultra DMA data-in burst) 18
(Initialing an Ultra DMA data-out data burst) (Sustained Ultra DMA data-out burst) 19
(Host terminating an Ultra DMA data-out burst) (Device terminating an Ultra DMA data-out burst) 20
3.4 Power Management (Ta = 0 to 700C) System Power Consumption: Symbol Parameter Conditions MIN TYP MAX Unit Iccr Read current 5V - 75 - mA Iccw Write current 5V - 75 - mA Ipd Power down current 5V - - 0.4 mA Iccr Read current 3.3V - 55 - mA Iccw Write current 3.3V - 55 - mA Ipd Power down current 3.3V - - 0.3 mA 4.0 Software Interface 4.
4.2 Command Sets Below table summarizes the PATA MINI PCIE command set with the paragraphs that follow describing the individual commands and task file for each command. No.
4.3 Identify Drive Information The Identity Drive Command enables Host to receive parameter information from the device. The parameter words in the buffer have the arrangement and meanings defined in below table. All reserve bits or words are zero.
Word Address Default Value Total Bytes Data Field Type Information Current capacity in sectors (LBAs)(Word 57= LSW, 57-58 Nnnnh 4 Word 58= MSW) 59 0101h 2 Multiple sector setting is valid 60-61 Aaaah 4 Total number of sectors addressable in LBA Mode 62 0000h 2 Retired 63 0n07h 2 Multiword DMA mode 2 and below are supported 64 0003h 2 Advance PIO transfer modes supported 65 0078h 2 Minimum Multiword DMA transfer cycle time 120nsec Manufacturer’s recommended Multiword DMA 66 0078h
5.0 Physical Dimension Top View Side & Bottom View Note: 1. Unit: mm General Tolerance: ± 0.1 6.0 Weight 1) 4 TSOP Flash: 6.8g 2) 2 TSOP Flash: 5.7g 3) 1 TSOP Flash: 4.
