Features: Standard ATA/IDE Bus Interface - 512 Bytes / Sector - ATA command set compatible Capacities - Integral Z Series (MLC): 32GB, 64GB, 128GB - Integral E Series (SLC): 4GB, 8GB, 16GB (Pls call for availability) Data Transfer mode - Support Data Transfer up to PIO mode 6 - Support Data Transfer up to Multiword DMA mode 2 - Support Data Transfer up to Ultra DMA mode 5 Performance Integral Z Series (MLC Flash) Sustain Read Speed up to 70 MB/s Sustain Write Speed up to 35
TABLE OF CONTENTS 1.0 BLOCK DIAGRAM ........................................................................................................................... 4 1.1 CAPACITY SPECIFICATION.................................................................................................... 4 2.0 SPECIFICATION ........................................................................................................................ 5 2.1 PIN ASSIGNMENTS..........................................................
1.0 Block Diagram 1.
2.0 Specification 2.1 Pin Assignments 2.2 Pin Description Pin No. Signal I/O* Description 03 -RESET I Hardware reset signal from the host 19, 17, 15, 13, 11, DD0~DD15(Device Data) I/O 16-bit bi-direction Data Bus. DD(7:0) are 09, 07, 05. 06, 08, used for 8-bit register transfers. 10, 12, 14, 16, 18, 20 22 DMARQ(DMA Request) O For DMA data transfers. Device will assert DMARQ when the device is ready to transfer data to or from the host.
27 IORDY(I/O channel ready) O This signal is used to temporarily stop the host register access (read or write) when the device is not ready to respond to a data transfer request. DDMARDY(UDMA ready) The device will assert this signal to indicate that the device is ready to receive UDMA data-out burst. DSTROBE(UDMA data When UDMA mode DMA Read is active, strobe) this signal is the data-in strobe generated by the device.
3.0 Electrical Characteristics 3.1 Absolute Maximum Rating Item Symbol Parameter MIN MAX Unit 1 VDD-VSS DC Power Supply -0.3 +5.5 V 2 VIN Input Voltage Vss-0.3 VDD+0.3 V 3 Ta Operating Temperature 0 +70 0 -25 +85 0 -40 +85 0 -40 +85 0 C (commercial) 4 Tst Storage Temperature C (commercial) 5 Ta Operating Temperature C (extensive) 6 Tst Storage Temperature C (extensive) Parameter Symbol MIN TYP MAX Unit VDD Voltage VDD 3.0 3.3 3.6 V 4.5 5.0 5.
3.3 AC Characteristics 3.3.
PIO timing parameters t0 Cycle time t1 Address valid to (min) DIOR-/DIOW- setup (min) t2 DIOR-/DIOW- (min) t2i DIOR-/DIOW- recovery time Mode 0 Mode 1 Mode2 Mode 3 Mode 4 Note ns ns ns ns ns 600 383 240 180 120 70 50 30 30 25 165 125 100 80 70 1 -- -- -- 70 25 1 1,4 (min) t3 DIOW- data setup (min) 60 45 30 30 20 t4 DIOW- data hold (min) 30 20 15 10 10 t5 DIOR- data setup (min) 50 35 20 20 20 t6 DIOR- data hold (min) 5 5 5 5 5 t6z
and DA(2:0) do change between read or write cycles. 3.3.
(Device terminating a Multiword DMA data burst) (Host terminating a Multiword DMA data burst) 11
Multiword DMA timing parameters Mode 0 Mode 1 Mode2 ns ns ns Note t0 Cycle time (min) 480 150 120 See note tD DIOR-/DIOW- asserted pulse width (min) 215 80 70 See note tE DIOR- data access (max) 150 60 50 tF DIOR- data hold (min) 5 5 5 tG DIOR-/DIOW- data setup (min) 100 30 20 tH DIOW- data hold (min) 20 15 10 tI DMACK to DIOR-/DIOW- setup (min) 0 0 0 tJ DIOR-/DIOW- to DMACK hold (min) 20 5 5 tKR DIOR- negated pulse width (min) 50 50 25 See not
3.3.
Ultra DMA data burst timing descriptions 14
(Initialing an Ultra DMA data-in burst) (Sustained Ultra DMA data-in burst) 15
(Device terminating an Ultra DMA data-in burst) (Host terminating an Ultra DMA data-in burst) 16
(Initialing an Ultra DMA data-out data burst) (Sustained Ultra DMA data-out burst) 17
(Host terminating an Ultra DMA data-out burst) (Device terminating an Ultra DMA data-out burst) 18
3.4 Power Management (Ta = 0 to 700C) System Power Consumption: Symbol Parameter Conditions MIN TYP MAX Unit Iccr Read current 3.3V - 160 - mA Iccw Write current 3.3V - 220 - mA Ipd Power down current 3.3V - - 0.3 mA **Note: Based on 32GB (4 uLGA Flash) 4.0 Software Interface 4.
5 CFA Write Sector w/o Erase 38h -- Y Y Y Y Y Y 6 Check Power Mode E5h -- -- -- -- Y -- -- 7 Execute Device Diagnostic 90h -- -- -- -- Y -- -- 8 Identify Device ECh -- -- -- -- Y -- -- 9 Idle E3h -- Y -- -- Y -- -- 10 Idle Immediate E1h -- -- -- -- Y -- -- 11 Initialize Device Parameters 91h -- Y -- -- Y Y -- 12 NOP 00h -- -- -- -- Y -- -- 13 Read Buffer E4h -- -- -- -- Y -- -- 14 Read DMA C8h -- Y Y Y Y Y Y
4.3 Identify Drive Information The Identity Drive Command enables Host to receive parameter information from the device. The parameter words in the buffer have the arrangement and meanings defined in below table. All reserve bits or words are zero.
Current capacity in sectors (LBAs)(Word 57= LSW, 57-58 xxxxh 4 Word 58= MSW) 59 0101h 2 Multiple sector setting is valid 60-61 xxxxh 4 Total number of sectors addressable in LBA Mode 62 0000h 2 Retired 63 0007h 2 Multiword DMA mode 2 and below are supported 64 0003h 2 Advance PIO transfer modes supported 65 0078h 2 Minimum Multiword DMA transfer cycle time 120nsec Manufacturer’s recommended Multiword DMA 66 0078h 2 transfer cycle time 120nsec Minimum PIO transfer cycle time witho
5.0 Physical Dimension 1) 4 uLGA flash for 32GB/64GB – PS3007/PS3016-P7 Top View Side & Bottom View Note: Unit: mm General Tolerance: ± 0.1 uLGA flash thickness: 64GB: 1.40mm; 32GB: 1.
Top View Side & Bottom View Note: 1. Unit: mm General Tolerance: ± 0.
