User's Manual
Table Of Contents
- 1.0 General Device Overview
- 2.0 Basic Operating Information
- 3.0 eUniStone Interfaces
- 4.0 General Device Capabilities
- 5.0 Bluetooth Capabilities
- 6.0 Electrical Characteristics
- 7.0 Package Information
- 8.0 Bluetooth Qualification and Regulatory Certification
- 8.1 Reference Design
- 8.2 FCC Class B Digital Devices Regulatory Notice
- 8.3 FCC Wireless Notice
- 8.4 FCC Interference Statement
- 8.5 FCC Identifier
- 8.6 European R&TTE Declaration of Conformity
- 8.7 Bluetooth Qualified Design ID
- 8.8 Industry Canada Certification
- 8.9 Label Design of the Host Product
- 8.10 Regulatory Test House
- 9.0 Assembly Guidelines
- References
- Terminology
eUniStone
PBA 31309
General Device Overview
User’s Manual Intel Public 11
Hardware Description Revision 1.0, 1-Feb-2013
1.4 Pin Description
The non-shaded cells indicate pins that will be fixed for the product lifetime. Shaded
cells indicate that the pin might be removed/changed in future variants. Pins not listed
below shall not be connected.
Table 1. Pin Description
Pin
No.
Symbol Input /
Output
Supply Voltage During
Reset
After
Reset
Function
A2 P1.6 I/O/OD Internal1 Z Z Port 1.6
A3 RESET# AI Internal1 Input Input Hardware Reset
A8 P1.5 I/O/OD Internal1 Input Input Port 1.5
B1 P1.7 I/O/OD Internal1 PD/ Input PD/ Input Port 1.7
B2 P1.8 I/O/OD Internal1 PD PD Port 1.8
B3 P1.0 /
TMS
I/O/OD Internal2 PU
1
PU
1.
Port 1.0 or
JTAG interface
B4 P1.4 /
RTCK
I/O/OD Internal2 Z Z Port 1.4 or
JTAG interface
B5 ONOFF I - - Turns off module completely
B9 P0.15 I/O VDDUART PD H Port 0.15
C2 P0.9 I/O/OD Internal2 Z Z Port 0.9
C3 JTAG# I Internal2 PU PU Mode selection Port 1:
0: JTAG
1: Port
C4 TRST# I Internal2 PD PD JTAG interface
D1 P0.10 I/O/OD Internal2 Z Z Port 0.10
D2 P0.8 I/O/OD Internal2 PD PD Port 0.8
D3 P1.1 /
TCK
I/O/OD Internal2 PU
1.
PU
1.
Port 1.1 or
JTAG interface
D4 P0.3 I/O/OD VDD1 Conf.
PD def.
Conf.
PD def.
Port 0.3
D5 P0.2 I/O/OD VDD1 Z Z Port 0.2
E1 P0.12 / SDA0 I/O/OD Internal2 PU PU I2C data signal
E2 P0.13 / SCL0 I/O/OD Internal2 PU PU I2C clock signal
E3 P1.3 /
TDO
I/O/OD Internal2 Z Z Port 1.3 or
JTAG interface
E4 P0.0 LPMout I/O/OD VDD1 PD PD Port 0.0
LPM wakeup output
E5 P0.1 I/O/OD VDD1 PD PD Port 0.1
E6 P0.5 /
UARTRXD
I/O/OD VDDUART Z Z Port 0.5 or
UART receive data
F2 P1.2 /
TDI
I/O/OD Internal2 PU
1.
PU
1.
Port 1.2 or
JTAG interface
F3 P0.11 I/O/OD Internal2 Z Z Port 0.11
F4 P0.14 LPMin I/O VDDUART Z Z Port 0.14
LPM wakup input
F5 P0.7 /
UARTCTS
I/O/OD VDDUART Z Z Port 0.7 or
UART CTS flow control
F7 P0.4 /
UARTTXD
I/O/OD VDDUART PU PU Port 0.4 or
UART transmit data
F8 P0.6 /
UARTRTS
I/O/OD VDDUART PU PU Port 0.6 or
UART RTS flow control
A4,
A5,
A6
VSUPPLY SI - - Power supply
C1VREG SO --Regulated Power supply
F6 VDDUART SI - - UART interface Power supply
C5 VDD1 SI - - Power supply