Intel® Core™2 Duo Processors and Intel® Core™2 Extreme Processors for Platforms Based on Mobile Intel® 965 Express Chipset Family Datasheet January 2008 Document Number: 316745-005
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Contents 1 Introduction .............................................................................................................. 7 1.1 Terminology ....................................................................................................... 8 1.2 References ......................................................................................................... 9 2 Low Power Features ................................................................................................ 11 2.
Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 Core Low Power States..............................................................................................12 Package Low Power States.........................................................................................13 Active VCC and ICC Loadline Intel Core 2 Duo Processors - Standard Voltage, Low Voltage and Ultra Low Voltage and Intel Core 2 Extreme Processors | (PSI# Not Asserted) .......................................................................
Revision History Document Number Revision Number 316745 -001 Description • Initial Release Date May 2007 • Updates 316745 -002 — Chapter 1 added Intel® Core™2 Duo processor - Ultra Low Voltage information — Chapter 3 added Table 8 with Intel Core 2 Duo processor Ultra Low Voltage U7600 and U7500 specifications — Chapter 3 updated Figure 3 and 5 with Intel Core 2 Duo processor - Ultra Low Voltage information — Chapter 5 added Table 19 with Intel Core 2 Duo processor -Ultra Low Voltage U7600 and U750
Datasheet
Introduction 1 Introduction The Intel® Core™2 Duo processor on 65-nm process technology is the next generation high-performance, low-power processor based on the Intel® Core™ microarchitecture. The Intel Core 2 Duo processor supports the Mobile Intel® 965 Express Chipset and Intel® 82801HBM ICH8M Controller Hub Based Systems.
Introduction 1.1 Terminology Term 8 Definition # A “#” symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the “#” symbol implies that the signal is inverted.
Introduction 1.2 References Material and concepts available in the following documents may be beneficial when reading this document. Document Document Number1,2 Intel® Core™ 2 Duo Processors For Intel® Centrino® Duo Processor Technology Specification Update 314079 Mobile Intel® 965 Express Chipset Family Datasheet 316273 Mobile Intel® 965 Express Chipset Family Specification Update 316274 Intel® I/O Controller Hub 8 (ICH8)/ I/O Controller Hub 8M (ICH8M) Datasheet See http:// www.intel.
Introduction 10 Datasheet
Low Power Features 2 Low Power Features 2.1 Clock Control and Low Power States The processor supports low power states both at the individual core level and the package level for optimal power management. A core may independently enter the C1/AutoHALT, C1/MWAIT, C2, C3, and C4 low power states.
Low Power Features Figure 1.
Low Power Features Figure 2. Package Low Power States SLP# asserted STPCLK# asserted Stop Grant Normal DPSLP# asserted SLP# deasserted Deeper † Sleep Deep Sleep Sleep STPCLK# deasserted DPRSTP# asserted DPSLP# deasserted DPRSTP# deasserted Snoop Snoop serviced occurs Stop Grant Snoop † — Deeper Sleep includes the Deeper Sleep state and Intel Enhanced Deeper Sleep state. Table 1.
Low Power Features A System Management Interrupt (SMI) handler returns execution to either Normal state or the AutoHALT Powerdown state. See the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A/3B: System Programmer's Guide for more information. The system can generate a STPCLK# while the processor is in the AutoHALT Powerdown state. When the system deasserts the STPCLK# interrupt, the processor returns execution to the HALT state.
Low Power Features 2.1.2 Package Low Power State Descriptions 2.1.2.1 Normal State This is the normal operating state for the processor. The processor remains in the Normal state when at least one of its cores is in the C0, C1/AutoHALT, or C1/MWAIT state. 2.1.2.2 Stop-Grant State When the STPCLK# pin is asserted by the chipset, each core of the dual core processor enters the Stop-Grant state within 20-bus clocks after the response phase of the processor-issued Stop-Grant Acknowledge special bus cycle.
Low Power Features In the Sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. No transitions or assertions of signals (with the exception of SLP#, DPSLP# or RESET#) are allowed on the FSB while the processor is in Sleep state. Snoop events that occur while in Sleep state or during a transition into or out of Sleep state causes unpredictable behavior.
Low Power Features Exit from Deeper Sleep or Intel Enhanced Deeper Sleep state is initiated by DPRSTP# deassertion when either core requests a core state other than C4 or either core requests a processor performance state other than the lowest operating point. 2.1.2.6.
Low Power Features 2.2 Enhanced Intel SpeedStep® Technology The processor features Enhanced Intel SpeedStep Technology. Following are the key features of Enhanced Intel SpeedStep Technology: • Multiple voltage and frequency operating points provide optimal performance at the lowest power.
Low Power Features 2.2.1 Dynamic FSB Frequency Switching Dynamic FSB frequency switching effectively reduces the internal bus clock frequency in half to further decrease the minimum processor operating frequency from the Enhanced Intel SpeedStep Technology performance states and achieve the Super Low Frequency Mode (SuperLFM). This feature is supported at FSB frequencies of 800-MHz and does not entail a change in the external bus signal (BCLK) frequency.
Low Power Features The processor implements two software interfaces for requesting extended package low power states: MWAIT instruction extensions with sub-state hints and via BIOS by configuring MSR bits to automatically promote package low power states to extended package low power states. Extended Stop-Grant and Extended Deeper Sleep must be enabled via the BIOS for the processor to remain within specification.
Low Power Features consumption allows for leakage current reduction, which results in platform power savings and extended battery life. There is no platform-level change required to support this feature as long as the VR vendor supports the VID-x feature. 2.6 Processor Power Status Indicator (PSI-2) Signal The processor incorporates the PSI# signal that is asserted when the processor is in a reduced power consumption state.
Low Power Features 22 Datasheet
Electrical Specifications 3 Electrical Specifications 3.1 Power and Ground Pins For clean, on-chip power distribution, the processor has a large number of VCC (power) and VSS (ground) inputs. All power pins must be connected to VCC power planes while all VSS pins must be connected to system ground planes. Use of multiple power and ground planes is recommended to reduce I*R drop. The processor VCC pins must be supplied the voltage determined by the VID (Voltage ID) pins. 3.
Electrical Specifications Table 2. 24 Voltage Identification Definition (Sheet 2 of 4) VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC (V) 0 0 1 0 1 1 0 1.2250 0 0 1 0 1 1 1 1.2125 0 0 1 1 0 0 0 1.2000 0 0 1 1 0 0 1 1.1875 0 0 1 1 0 1 0 1.1750 0 0 1 1 0 1 1 1.1625 0 0 1 1 1 0 0 1.1500 0 0 1 1 1 0 1 1.1375 0 0 1 1 1 1 0 1.1250 0 0 1 1 1 1 1 1.1125 0 1 0 0 0 0 0 1.1000 0 1 0 0 0 0 1 1.0875 0 1 0 0 0 1 0 1.
Electrical Specifications Table 2. Datasheet Voltage Identification Definition (Sheet 3 of 4) VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC (V) 1 0 0 0 1 0 1 0.6375 1 0 0 0 1 1 0 0.6250 1 0 0 0 1 1 1 0.6125 1 0 0 1 0 0 0 0.6000 1 0 0 1 0 0 1 0.5875 1 0 0 1 0 1 0 0.5750 1 0 0 1 0 1 1 0.5625 1 0 0 1 1 0 0 0.5500 1 0 0 1 1 0 1 0.5375 1 0 0 1 1 1 0 0.5250 1 0 0 1 1 1 1 0.5125 1 0 1 0 0 0 0 0.
Electrical Specifications Table 2. 3.4 Voltage Identification Definition (Sheet 4 of 4) VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC (V) 1 1 1 0 1 0 0 0.0500 1 1 1 0 1 0 1 0.0375 1 1 1 0 1 1 0 0.0250 1 1 1 0 1 1 1 0.0125 1 1 1 1 0 0 0 0.0000 1 1 1 1 0 0 1 0.0000 1 1 1 1 0 1 0 0.0000 1 1 1 1 0 1 1 0.0000 1 1 1 1 1 0 0 0.0000 1 1 1 1 1 0 1 0.0000 1 1 1 1 1 1 0 0.0000 1 1 1 1 1 1 1 0.
Electrical Specifications 3.6 FSB Frequency Select Signals (BSEL[2:0]) The BSEL[2:0] signals are used to select the frequency of the processor input clock (BCLK[1:0]). These signals should be connected to the clock chip and the appropriate chipset on the platform. The BSEL encoding for BCLK[1:0] is shown in Table 3. Table 3. 3.
Electrical Specifications Table 4. FSB Pin Groups Signal Group Signals1 Type AGTL+ Common Clock Input Synchronous to BCLK[1:0] BPRI#, DEFER#, PREQ#5, RESET#, RS[2:0]#, TRDY# AGTL+ Common Clock I/O Synchronous to BCLK[1:0] ADS#, BNR#, BPM[3:0]#3, BR0#, DBSY#, DRDY#, HIT#, HITM#, LOCK#, PRDY#3, DPWR# Signals AGTL+ Source Synchronous I/O Synchronous to assoc.
Electrical Specifications 3.8 CMOS Signals CMOS input signals are shown in Table 4. Legacy output FERR#, IERR# and other nonAGTL+ signals (THERMTRIP# and PROCHOT#) utilize Open Drain output buffers. These signals do not have setup or hold time specifications in relation to BCLK[1:0]. However, all of the CMOS signals are required to be asserted for more than four BCLKs in order for the processor to recognize them. See Section 3.10 for the DC specifications for the CMOS signal groups. 3.
Electrical Specifications 3.10 Processor DC Specifications The processor DC specifications in this section are defined at the processor core (pads) unless noted otherwise. See Table 4 for the pin signal definitions and signal pin assignments. Table 6 through Table 8 list the DC specifications for the processor and are valid only while meeting specifications for junction temperature, clock frequency, and input voltages.
Electrical Specifications Table 6. Voltage and Current Specifications for the Intel Core 2 Duo Processors Standard Voltage (Sheet 2 of 2) Symbol Parameter Min Typ Max Unit Notes IDSLP ICC Deep Sleep HFM SuperLFM 25.0 16.0 A 3, 4, 12 IDPRSLP ICC Deeper Sleep 11.5 A 3, 4 IDC4 ICC Intel Enhanced Deeper Sleep 9.
Electrical Specifications Table 7. Voltage and Current Specifications for the Intel Core 2 Duo Processors - Low Voltage Symbol Parameter Min Typ Max Unit Notes 1.3000 V 1, 2 VCCDAM VCC in Intel® Dynamic Acceleration Technology Mode VCCHFM VCC at High Frequency Mode (HFM) 0.9000 1.2000 V 1, 2 VCCLFM VCC at Low Frequency Mode (LFM) 0.9000 1.0500 V 1, 2, 13 VCCSLFM VCC at Super Low Frequency Mode (SuperLFM) 0.7500 0.
Electrical Specifications 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. The voltage specifications are assumed to be measured across VCC_SENSE and VSS_SENSE pins at socket with a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-mΩ minimum impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled in the scope probe. Specified at 100°C Tj. Specified at the nominal VCC. 800-MHz FSB supported.
Electrical Specifications Table 8. Voltage and Current Specifications for the Intel Core 2 Duo -Ultra Low Voltage Processors (Sheet 2 of 2) Symbol Parameter Min Typ Max Unit Notes IDC4 ICC Intel Enhanced Deeper Sleep 4.0 A 3, 4 dICC/DT VCC Power Supply Current Slew Rate at Processor Package Pin 600 A/µs 7, 9 ICCA ICC for VCCA Supply 130 mA ICCP ICC for VCCP Supply before VCC Stable ICC for VCCP Supply after VCC Stable 4.5 2.5 A A 10 11 NOTES: 1.
Electrical Specifications Table 9. Voltage and Current Specifications for the Intel Core 2 Extreme Processors (Sheet 2 of 2) Symbol Parameter Min Typ Max Unit Notes 55 55 37 29 A 3, 4, 5, 11, 12 Extreme Processor ICC for the Processor Processor Number ICC X7900 X7800 Core Frequency/Voltage 2.80 2.60 1.20 0.80 GHz GHz GHz GHz & & & & VCCHFM VCCHFM VCCLFM VCCSLFM IAH, ISGNT ICC Auto-Halt & Stop-Grant HFM SuperLFM 29.8 21.6 A 3, 4 ISLP ICC Sleep HFM SuperLFM 29.1 21.
Electrical Specifications Figure 3. Active VCC and ICC Loadline Intel Core 2 Duo Processors - Standard Voltage, Low Voltage and Ultra Low Voltage and Intel Core 2 Extreme Processors (PSI# Not Asserted) VCC-CORE [V] Slope = -2.1 mV/A at package VccSense, VssSense pins. Differential Remote Sense required. VCC-CORE max {HFM|LFM} VCC-CORE, DC max {HFM|LFM} 10mV= RIPPLE VCC-CORE nom {HFM|LFM} VCC-CORE, DC min {HFM|LFM} VCC-CORE min {HFM|LFM} +/-VCC-CORE Tolerance = VR St. Pt.
Electrical Specifications Figure 4. Deeper Sleep VCC and ICC Loadline Intel Core 2 Duo Processors - Standard Voltage and Intel Core 2 Extreme Processors (PSI# Asserted) VCC-CORE[V] Slope = -2.1 mV/A at package VccSense, VssSense pins. Differential Remote Sense required. VCC-CORE max {Deeper Sleep} VCC-CORE, DC max {Deeper Sleep} 13mV= RIPPLE for PSI# Asserted VCC-CORE nom {Deeper Sleep} VCC-CORE, DC min {Deeper Sleep} VCC-CORE min {Deeper Sleep} +/-VCC-CORE Tolerance = VR St. Pt.
Electrical Specifications Figure 5. Deeper Sleep VCC and ICC Loadline Intel Core 2 Duo Processor - Low Voltage and Ultra Low Voltage (PSI# Asserted) NOTE: Deeper Sleep mode tolerance depends on VID value. Table 10. FSB Differential BCLK Specifications Symbol Parameter VCROSS Crossing Voltage ΔVCROSS Range of Crossing Points VSWING Differential Output Swing ILI Cpad Input Leakage Current Pad Capacitance Min Typ 0.3 Max Unit Notes1 0.55 V 2, 7, 8 140 mV 2, 7, 5 300 -5 0.95 1.
Electrical Specifications Table 11. AGTL+ Signal Group DC Specifications Symbol VCCP GTLREF RCOMP RODT Parameter I/O Voltage Min Typ Max Unit 1.00 1.05 1.10 V Reference Voltage Compensation Resistor 2/3 VCCP 27.23 Termination Resistor 27.5 27.78 55 Notes1 V 6 Ω 10 Ω 11 VIH Input High Voltage GTLREF+0.10 VCCP VCCP+0.10 V 3,6 VIL Input Low Voltage -0.10 0 GTLREF-0.10 V 2,4 VOH Output High Voltage VCCP-0.
Electrical Specifications Table 12. CMOS Signal Group DC Specifications Symbol VCCP Parameter I/O Voltage Min Typ Max Unit 1.00 1.05 1.10 V Notes1 VIH Input High Voltage 0.7*VCCP VCCP VCCP+0.1 V 2 VIL Input Low Voltage CMOS -0.10 0.00 0.3*VCCP V 2 VOH Output High Voltage 0.9*VCCP VCCP VCCP+0.1 V 2 VOL Output Low Voltage -0.10 0 0.1*VCCP V 2 IOH Output High Current 1.5 4.1 mA 5 IOL Output Low Current 1.5 4.
Package Mechanical Specifications and Pin Information 4 Package Mechanical Specifications and Pin Information 4.1 Package Mechanical Specifications The processor is available in 4-MB and 2-MB, 478-pin Micro-FCPGA packages as well as 4-MB and 2-MB, 479-ball Micro-FCBGA packages. The package mechanical dimensions, keep-out zones, processor mass specifications, and package loading specifications are shown in Figure 6 through Figure 13.
Package Mechanical Specifications and Pin Information Figure 6. 4-MB and Fused 2-MB Micro-FCPGA Processor Package Drawing (Sheet 1 of 2) h Bottom View Top View Front View Side View & ' %( ! "# $% $ ) P Detail A 42 + ,- 1--1 .0.2 1/ * * * * 1 1 1 1 1 1 )1.
Package Mechanical Specifications and Pin Information Figure 7. 4-MB and Fused 2-MB Micro-FCPGA Processor Package Drawing (Sheet 2 of 2) "# $ %& ' Side View ( ( $ %& ' Top View ø0.305±0.25 ø0.406 M C A B ø0.
Package Mechanical Specifications and Pin Information Figure 8. 2-MB Micro-FCPGA Processor Package Drawing (Sheet 1 of 2) Bottom View Top View Front View Side View & ' %( ! "# $% $ ) P Detail A 44 + , 1--1 .0.2 1/ * * , .
Package Mechanical Specifications and Pin Information Figure 9. 2-MB Micro-FCPGA Processor Package Drawing (Sheet 2 of 2) "# $ %& ' Side View ( ( $ %& ' Top View ø0.305±0.25 ø0.406 M C A B ø0.
Package Mechanical Specifications and Pin Information Figure 10. 4-MB and Fused 2-MB Micro-FCBGA Processor Package Drawing (Sheet 1 of 2) ' ' ' ' #' # Top View Bottom View !!" M Front View Detail B $ !% & Side View $( )% *+",- ,% .
Package Mechanical Specifications and Pin Information Figure 11.
Package Mechanical Specifications and Pin Information Figure 12. 2-MB Micro-FCBGA Processor Package Drawing (Sheet 1 of 2) ' ' ' ' #' # Top View Bottom View !!" M Front View Detail B $ !% & Side View $( )% *+",- ,% .
Package Mechanical Specifications and Pin Information Figure 13. 2-MB Micro-FCBGA Processor Package Drawing (Sheet 2 of 2) "# $ %& ' Side View ( ( $ %& ' Top View ! ! 4.2 Bottom View Processor Pinout and Pin List Table 14 shows the top view pinout of the Intel Core 2 Duo mobile processor. The pin list, arranged in two different formats, is shown in the following pages.
Package Mechanical Specifications and Pin Information Table 14.
Package Mechanical Specifications and Pin Information Table 15.
Package Mechanical Specifications and Pin Information This page is intentionally left blank.
Package Mechanical Specifications and Pin Information Table 16. Table 16.
Package Mechanical Specifications and Pin Information Table 16. Pin Listing by Pin Name (Sheet 3 of 16) Pin Number Signal Buffer Type Direction BR0# F1 Common Clock Input/ Output BSEL[0] B22 CMOS Output BSEL[1] B23 CMOS Output BSEL[2] C21 CMOS COMP[0] R26 COMP[1] Table 16.
Package Mechanical Specifications and Pin Information Table 16. Pin Listing by Pin Name (Sheet 5 of 16) Pin Number Signal Buffer Type Direction D[37]# T22 Source Synch Input/ Output D[38]# U25 Source Synch D[39]# U23 D[40]# Table 16.
Package Mechanical Specifications and Pin Information Table 16. Pin Listing by Pin Name (Sheet 7 of 16) Table 16.
Package Mechanical Specifications and Pin Information Table 16. Pin Listing by Pin Name (Sheet 9 of 16) Pin Number Signal Buffer Type VCC AA13 Power/Other VCC AA15 VCC Table 16.
Package Mechanical Specifications and Pin Information Table 16. Pin Listing by Pin Name (Sheet 11 of 16) Pin Number Signal Buffer Type VCC E12 Power/Other VCC E13 VCC Table 16.
Package Mechanical Specifications and Pin Information Table 16. Pin Listing by Pin Name (Sheet 13 of 16) Pin Number Signal Buffer Type VSS AC14 Power/Other VSS AC16 VSS Table 16.
Package Mechanical Specifications and Pin Information Table 16. Pin Listing by Pin Name (Sheet 15 of 16) Pin Number Signal Buffer Type VSS F16 Power/Other VSS F19 VSS F22 Pin Name Table 16.
Package Mechanical Specifications and Pin Information Table 17. Pin Listing by Pin Number (Sheet 2 of 17) Pin Number Signal Buffer Type VSS A8 Power/Other VCC A9 VCC A10 Pin Name Table 17.
Package Mechanical Specifications and Pin Information Table 17.
Package Mechanical Specifications and Pin Information Table 17. Pin Listing by Pin Number (Sheet 6 of 17) Pin Number Signal Buffer Type Direction VID[2] AE5 CMOS Output PSI# AE6 CMOS VSSSENSE AE7 Power/Other Pin Name Table 17.
Package Mechanical Specifications and Pin Information Table 17. Pin Listing by Pin Number (Sheet 8 of 17) Pin Number Signal Buffer Type Direction BSEL[0] B22 CMOS Output BSEL[1] B23 CMOS Output VSS B24 Pin Name Table 17.
Package Mechanical Specifications and Pin Information Table 17. Pin Listing by Pin Number (Sheet 10 of 17) Pin Number Signal Buffer Type VCC E12 Power/Other VCC E13 VSS Table 17.
Package Mechanical Specifications and Pin Information Table 17. Pin Listing by Pin Number (Sheet 12 of 17) Pin Number Signal Buffer Type VSS H6 Power/Other VSS H21 Power/Other D[12]# H22 Source Synch Pin Name Direction Input/ Output Input/ Output D[15]# H23 Source Synch VSS H24 Power/Other DINV[0]# H25 Source Synch Input/ Output Table 17.
Package Mechanical Specifications and Pin Information Table 17.
Package Mechanical Specifications and Pin Information Table 17.
Package Mechanical Specifications and Pin Information 4.3 Alphabetical Signals Reference Table 18. Signal Description (Sheet 1 of 7) Name A[35:3]# A20M# Type Description Input/ Output A[35:3]# (Address) define a 236-byte physical memory address space. In subphase 1 of the address phase, these pins transmit the address of a transaction. In sub-phase 2, these pins transmit transaction type information. These signals must connect the appropriate pins of both agents on the processor FSB.
Package Mechanical Specifications and Pin Information Table 18. Name Signal Description (Sheet 2 of 7) Type Description BSEL[2:0] Output BSEL[2:0] (Bus Select) are used to select the processor input clock frequency. Table 3 defines the possible combinations of the signals and the frequency associated with each combination. The required frequency is determined by the processor, chipset and clock synthesizer. All agents must operate at the same frequency.
Package Mechanical Specifications and Pin Information Table 18. Name Signal Description (Sheet 3 of 7) Type Description DINV[3:0]# (Data Bus Inversion) are source synchronous and indicate the polarity of the D[63:0]# signals. The DINV[3:0]# signals are activated when the data on the data bus is inverted. The bus agent inverts the data bus signals if more than half the bits, within the covered group, would change level in the next cycle.
Package Mechanical Specifications and Pin Information Table 18. Name FERR#/PBE# Signal Description (Sheet 4 of 7) Type Output Description FERR# (Floating-point Error)/PBE#(Pending Break Event) is a multiplexed signal and its meaning is qualified with STPCLK#. When STPCLK# is not asserted, FERR#/ PBE# indicates a floating point when the processor detects an unmasked floatingpoint error.
Package Mechanical Specifications and Pin Information Table 18. Name LINT[1:0] Signal Description (Sheet 5 of 7) Type Description Input LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all APIC Bus agents. When the APIC is disabled, the LINT0 signal becomes INTR, a maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable interrupt. INTR and NMI are backward compatible with the signals of those names on the Intel® Pentium® processor. Both signals are asynchronous.
Package Mechanical Specifications and Pin Information Table 18. Name Signal Description (Sheet 6 of 7) Type Description RESET# Input Asserting the RESET# signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents. For a power-on Reset, RESET# must stay active for at least two milliseconds after VCC and BCLK have reached their proper specifications. On observing active RESET#, both FSB agents deasserts their outputs within two clocks.
Package Mechanical Specifications and Pin Information Table 18. Name Signal Description (Sheet 7 of 7) Type Description Output The processor protects itself from catastrophic overheating by use of an internal thermal sensor. This sensor is set well above the normal operating temperature to ensure that there are no false trips. The processor stops all execution when the junction temperature exceeds approximately 125°C. This is signalled to the system by the THERMTRIP# (Thermal Trip) pin.
Package Mechanical Specifications and Pin Information 76 Datasheet
Thermal Specifications and Design Considerations 5 Thermal Specifications and Design Considerations Maintaining the proper thermal environment is key to reliable, long-term system operation. A complete thermal solution includes both component and system level thermal management features.
Thermal Specifications and Design Considerations 5. 6. 7. 8. 9. 10. Processor TDP requirements in Intel Dynamic Acceleration Technology mode is lesser than TDP in HFM. At Tj of 100oC At Tj of 50oC At Tj of 35oC 4-M L2 cache 2-M L2 cache Table 20. Symbol TDP Power Specifications for the Intel Core 2 Duo Processor - Low Voltage Processor Number PSGNT Thermal Design Power L7700 1.8 GHz & HFM VCC 17 L7500 1.6 GHz & HFM VCC 17 L7300 1.4 GHz & HFM VCC 17 1.2 GHZ & LFM VCC 16.1 0.
Thermal Specifications and Design Considerations Table 21. Symbol TDP Power Specifications for the Intel Core 2 Duo Processor - Ultra Low Voltage Processor Number PSGNT Thermal Design Power U7700 1.33 GHz & HFM VCC 10 U7600 1.20 GHz & HFM VCC 10 U7500 1.06 GHz & HFM VCC 10 0.80 GHZ & LFM VCC 9.2 Symbol PAH, Core Frequency & Voltage Parameter Min Typ Unit Notes W 1, 4, 5, 6, 9 Max Unit at HFM VCC 3.1 W 2, 5, 7 at LFM VCC 2.
Thermal Specifications and Design Considerations Table 22. Symbol TDP Power Specifications for the Intel Core 2 Extreme Processor Processor Number PSGNT Thermal Design Power X7900 2.8 GHz & HFM VCC 44 X7800 2.6 GHz & HFM VCC 44 1.2 GHZ & LFM VCC 35 0.80 GHZ & SuperLFM VCCc 27 Symbol PAH, Core Frequency & Voltage Parameter Min Typ Unit Notes W 1, 4, 5, 6, 9 Max Unit 15.7 W 2, 5, 7 W 2, 5, 7 W 2, 5, 8 Auto Halt, Stop Grant Power at HFM VCC at SuperLFM VCC 9.
Thermal Specifications and Design Considerations 5.1.1 Thermal Diode The processor incorporates an on-die PNP transistor whose base emitter junction is used as a thermal diode, with its collector shorted to ground. The thermal diode can be read by an off-die analog/digital converter (a thermal sensor) located on the motherboard or a stand-alone measurement kit.
Thermal Specifications and Design Considerations Table 24. Thermal Diode Parameters Using Diode Model Symbol IFW Parameter Min Typ Max Unit Notes 200 µA 1 Ω 2, 3, 5 Forward Bias Current 5 n Diode Ideality Factor 1.000 1.009 1.050 RT Series Resistance 2.79 4.52 6.24 2, 3, 4 NOTES: 1. Intel does not support or recommend operation of the thermal diode under reverse bias.
Thermal Specifications and Design Considerations Table 25. Thermal Diode Parameters Using Transistor Model Symbol Parameter Min IFW Forward Bias Current IE Emitter Current nQ Transistor Ideality 5 5 0.997 Beta RT Typ 1.001 0.3 Series Resistance 2.79 4.52 Max Unit Notes 200 μA 1,2 200 μA 1 1.005 3,4,5 0.760 3,4 6.24 Ω 3,6 NOTES: 1. Intel does not support or recommend operation of the thermal diode under reverse bias. 2. Same as IFW in Table 24. 3.
Thermal Specifications and Design Considerations If the ntrim value used to calculate the Toffset differs from the ntrim value used to in a temperature sensing device, the Terror(nf) may not be accurate. If desired, the Toffset can be adjusted by calculating nactual and then recalculating the offset using the ntrim as defined in the temperature sensor manufacturer’s datasheet. The ntrim used to calculate the Diode Correction Toffset are listed in Table 26. Table 26. 5.1.
Thermal Specifications and Design Considerations EMTTM is a processor feature that enhances Intel Thermal Monitor 2 with a processor throttling algorithm known as Adaptive Intel Thermal Monitor 2. Adaptive Intel Thermal Monitor 2 transitions to intermediate operating points, rather than directly to the LFM, once the processor has reached its thermal limit and subsequently searches for the highest possible operating point. Please ensure this feature is enabled and supported in the BIOS.
Thermal Specifications and Design Considerations junction temperature within the maximum specification, the system must initiate an orderly shutdown to prevent damage. If the processor enters one of the above low power states with PROCHOT# already asserted, PROCHOT# will remain asserted until the processor exits the low power state and the processor junction temperature drops below the thermal trip point.
Thermal Specifications and Design Considerations 5.1.5 Out of Specification Detection Overheat detection is performed by monitoring the processor temperature and temperature gradient. This feature is intended for graceful shut down before the THERMTRIP# is activated. If the processor’s Intel Thermal Monitor 1 or 2 are triggered and the temperature remains high, an “Out Of Spec” status and sticky bit are latched in the status MSR register and generates thermal interrupt. 5.1.
