21555 Non-Transparent PCI-toPCI Bridge User Manual July 2001 Order Number: 278321–002
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Contents Contents 1 Preface ..........................................................................................................................................11 1.1 1.2 1.3 1.4 1.5 2 Introduction....................................................................................................................................15 2.1 2.2 2.3 2.4 3 Primary PCI Bus Interface Signals .....................................................................................
Contents 5.2 5.3 5.4 5.5 5.6 5.7 6 Initialization Requirements ............................................................................................................ 65 6.1 6.2 6.3 6.4 6.5 7 Interface Signals ................................................................................................................. 81 Parallel and Serial ROM Connection .................................................................................. 84 PROM Read by CSR Access ..........................
Contents 9.2 9.3 9.4 10 Arbitration ......................................................................................................................................97 10.1 10.2 10.3 10.4 11 12.2 12.3 Inbound Message Passing ...............................................................................................113 Outbound Message Passing.............................................................................................115 Notes ...................................................
Contents 16.7 16.8 16.9 16.10 16.11 16.12 16.13 16.14 16.15 Interrupt Registers ............................................................................................................ 170 Scratchpad Registers ....................................................................................................... 174 PROM Registers............................................................................................................... 175 SROM Registers............................................
Contents 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 Primary PCI Bus Interface 64-Bit Extension Signals ..................................................................26 Secondary PCI Bus Interface Signals.........................................................................................28 Secondary PCI Bus Interface 64-Bit Extension Signals ......................................................
Contents 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 8 Primary Interface Configuration Space Address Map .............................................................. 148 Secondary Interface Configuration Space Address Map.......................................................... 148 Vendor ID Register ...........................................................................................
Contents 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 Primary Expansion ROM BAR..................................................................................................175 Primary Expansion ROM Setup Register .................................................................................176 ROM Setup Register.................................................................................................................
1 Preface A brief description of the contents of this manual follows. Chapter 1, “Preface” Provides information about the contents and organization of this book. Chapter 2, “Introduction” Provides an overview of the 21555 functionality and architecture. Chapter 3, “Signal Descriptions” Describes PCI signal pins grouped by function. Chapter 4, “Address Decoding” Contains details about how addresses are decoded.
Preface 1.1 Cautions and Notes Caution: Note: 1.2 Cautions provide information to prevent damage to equipment or loss of data. Notes emphasize particularly important information. Data Units This manual uses the following data-unit terminology. 1.3 Term Words Bytes Bits Byte ½ 1 8 Word 1 2 16 Dword 2 4 32 Quadword 4 8 64 Numbering All numbers are decimal unless appended with a radix specifier. • “h” is the hexadecimal radix. • “b” is the binary radix.
Preface 1.4 Signal Nomenclature 21555 device signal names are printed in lowercase type. Prefixes and suffixes are tagged with a leading or trailing letter and are delimited with an “_” underscore: • • • • The prefix “p_” denotes a primary bus signal. For example: p_ad is the primary interface address/data bus. The prefix “s_” denotes a secondary bus signal. For example: s_ad is the secondary interface address/data bus. Other prefixes might appear. l_(load), pr_(parallel rom), and so on.
Preface 1.5 Register Abbreviations When a register is associated with the primary interface, its name is preceded with Primary. When a register is associated with the secondary interface, its name is preceded with Secondary. When a register is shared by both interfaces, it is not preceded with Primary or Secondary. The byte offsets at which each register can be accessed from each interface are listed in each register description. Table 2 lists the register access abbreviations. Table 2.
Introduction 2 The Intel® 21555 is a PCI peripheral device that performs PCI bridging functions for embedded and intelligent I/O applications. The 21555 has a 64-bit primary interface, a 64-bit secondary interface, and 66-MHz capability. In this document the 21555 non-transparent device is compared to the related 21154 transparent devices. Both devices have similar operating characteristic. The 21555 is a “non-transparent” PCI-to-PCI Bridge (PPB) that acts as a gateway to an intelligent subsystem.
Introduction A primary goal of the PPB architecture is that PPB are transparent to devices and device drivers. For example, no changes are needed to a device driver when a PCI peripheral is located behind a PPB. Once configured during system initialization, a PPB operates without the aid of a device driver. A PPB does not require a device driver of its own since it does not have any resources that must be managed by software during run-time.
Introduction Table 3 shows compares a 21555 and to a transparent PPB. Table 3. 21555 and PPB Feature Comparison Feature Non-Transparent PPB or 21555 Transparent PPB • Adheres to PPB ordering rules. Transaction forwarding Address decoding • Uses posted writes and delayed transactions. • Adheres to PPB transaction error and parity error guidelines, although some errors may be reported differently. • Base address registers (BARs) are used to define independent downstream and upstream forwarding windows.
Introduction 2.2 Architectural Overview This section describes the buffers, registers, and control logic of the 21555: 2.2.1 Data Buffers Data buffers include the buffers along with the associated data path control logic. Delayed transaction buffers contain the compare functionality for completing delayed transactions. The blocks also contain the watchdog timers associated with the buffers. The data buffers are as follows: • • • • • • • Four-entry downstream delayed transaction buffer.
Introduction Figure 2 shows the 21555 microarchitecture. Figure 2.
Introduction 2.3 Special Applications 2.3.1 Primary Bus VGA Support The 21555 provides hardware support that allows configuration of itself as a Video Graphics Adapter (VGA) device. The primary class code should be preloaded through the serial ROM (SROM) or loaded by the local processor with the value for a VGA device (Base Class 03h, Sub-Class 00h, Programming Interface 00h). This allows the 21555 to present itself to the host as a VGA device.
Introduction • Setting a translated base address for a downstream range to fall within an address range defined for upstream forwarding. This would cause the 21555 to respond as a target on the secondary bus to a downstream transaction that it has initiated as a master. The transaction would then be forwarded back to the primary bus. The address on the primary bus depends on the translated base address value for that upstream range.
3 Signal Descriptions This chapter presents the theory of operation information about the PCI signal interface. See Chapter 16 for specific information about PCI registers. Table 5 describes the PCI signal groups, function, and provides a page reference. Table 5. Signal Pin Functional Groups Group by Signal Pin Description See Page All PCI pins required by the PCI Local Bus Specification, Revision 2.2. Section 3.
Signal Descriptions 3.1 Primary PCI Bus Interface Signals Table 6 describes the primary PCI bus interface signals. The letters in the “Type” column are described in Table 1. Table 6. Primary PCI Bus Interface Signals (Sheet 1 of 2) Signal Name p_ad[31:0] Type TS Description Primary PCI interface address and data. These signals are a 32-bit multiplexed address and data bus. During the address phase or phases of a transaction, the initiator drives a physical address on p_ad[31:0].
Signal Descriptions Table 6. Primary PCI Bus Interface Signals (Sheet 2 of 2) Signal Name p_par Type TS Description Primary PCI interface parity. Signal p_par carries the even parity of the 36 bits of p_ad[31:0] and p_cbe_l[3:0] for both address and data phases. Signal p_par is driven by the same agent that drives the address (for address parity) or the data (for data parity).
Signal Descriptions 3.2 Primary PCI Bus Interface 64-Bit Extension Signals Table 7 describes the primary PCI bus interface 64-bit extension signals. The letters in the “Type” column are described in Table 1. Table 7. Primary PCI Bus Interface 64-Bit Extension Signals (Sheet 1 of 2) Signal Name Type Description Primary PCI interface acknowledge 64-bit transfer. Signal p_ack64_l should never be driven when p_req64_l is not driven.
Signal Descriptions Table 7. Primary PCI Bus Interface 64-Bit Extension Signals (Sheet 2 of 2) Signal Name Type Description Primary PCI interface upper 32 bits parity. The 21555 does not bus park this pin. This pin is tristated during the assertion of p_rst_l. Signal p_par64 is driven to a valid value when the 64-bit extension is disabled (p_req64_l is deasserted during p_rst_l assertion).
Signal Descriptions 3.3 Secondary PCI Bus Interface Signals Table 8 describes the secondary PCI bus interface signals. The letters in the “Type” column are described in Table 1. Table 8. Secondary PCI Bus Interface Signals (Sheet 1 of 2) Signal Name s_ad[31:0] Type TS Description Secondary PCI interface address and data. These signals are a 32-bit multiplexed address and data bus. During the address phase or phases of a transaction, the initiator drives a physical address on s_ad[31:0].
Signal Descriptions Table 8. Secondary PCI Bus Interface Signals (Sheet 2 of 2) Signal Name s_par Type TS Description Secondary PCI interface parity. Signal s_par carries the even parity of the 36 bits of s_ad[31:0] and s_cbe_l[3:0] for both address and data phases. Signal s_par is driven by the same agent that drives the address (for address parity) or the data (for data parity).
Signal Descriptions 3.4 Secondary PCI Bus Interface 64-Bit Extension Signals Table 9 describes the secondary PCI bus interface 64-bit extension signals. The letters in the “Type” column are described in Table 1. Table 9. Secondary PCI Bus Interface 64-Bit Extension Signals (Sheet 1 of 2) Signal Name Type Description Secondary PCI interface acknowledge 64-bit transfer. Signal s_ack64_l should never be driven when s_req64_l is not driven.
Signal Descriptions Table 9. Secondary PCI Bus Interface 64-Bit Extension Signals (Sheet 2 of 2) Signal Name Type Description Secondary PCI interface upper 32 bits parity. The 21555 does not bus park this pin. This pin is tristated during the assertion of s_rst_l. Signal s_par64 is driven to a valid value when the 64-bit extension is disabled (s_req64_l is deasserted during s_rst_l assertion).
Address Decoding 4 This chapter presents the theory of operation information about address mapping and decoding. See Chapter 16 for specific information about addressing registers. The following areas are covered: • • • • • Section 4.1, “CSR Address Decoding” on page 34. Section 4.2, “Expansion ROM Address Mapping (Decoding)” on page 34. Section 4.3, “Memory 0 Transaction Address Decoding” on page 34. Section 4.4, “I/O Transaction Address Decoding” on page 42. Section 4.
Address Decoding 4.1 CSR Address Decoding The 21555 implements a set of CSRs that are mapped in memory or in I/O space. The registers are mapped independently on the primary and secondary interfaces. The following BARs are used for CSR mapping: • The primary CSR and: — Downstream Memory 0 BAR is for mapping in primary bus memory address space. The Lower 4KB of this range used to map the 21555 CSRs. — I/O BAR is for mapping in primary bus I/O space.
Address Decoding 4.3.1 Using the BAR Setup Registers All downstream and upstream BARs have programmable sizes, and can be disabled so that they request no space. The Primary CSR and Downstream Memory 0 BAR cannot be totally disabled, as the 21555 CSRs are always mapped in the bottom 4KB. The forwarding part of the range can be disabled by requesting only 4KB of memory Table 12 on page 47 summarizes the minimum and maximum range for each address range).
Address Decoding 4.3.2 Direct Address Translation With the exception of secondary bus transactions falling into the Upstream Memory 2 address range (see Section 4.3.3) and all dual address transactions (Section 4.3.5), the 21555 uses direct address translation when forwarding memory transactions from one interface to the other.
Address Decoding This new base address, also called the translated base address, references a new location in the secondary bus address map. The offset is not affected. The process is similar for transactions forwarded from the secondary bus to the primary bus. Figure 5. Direct Offset Address Translation Base Offset Original Address Translated Base Offset Translated Address A7463-01 Each memory address range using direct offset address translation has its own translated base.
Address Decoding The Upstream Memory 2 address range consists of a fixed number (64) of pages. The page size is programmable in the Chip Control 1 configuration register. Therefore, the size of the Upstream Memory 2 BAR is dependent on the page size. The page size varies between 256 bytes to 32 MB by powers of 2. This results in a window size that varies from 16 KB to 2 GB. This BAR can also be disabled. Each page of the upstream window has a corresponding translated base address.
Address Decoding Figure 7 shows how a translated address is built using the lookup table, assuming a page size of 4 KB. Figure 7.
Address Decoding Note: The indirect access mechanism must be used only by one interface at a time. When access to the lookup table by multiple masters is possible, it is strongly recommended that the Generic Own bits or some other semaphore mechanism be used to restrict access to one master at a time. Figure 8.
Address Decoding Note: The lookup table is not cleared by reset. The lookup table must be initialized by the local processor before the Upstream Memory 2 Address range is used. Figure 9. Lookup Table Entry Format 31 18 17 Translated Base Address 8 7 Translated Base Address or Reserved 4 3 2 1 0 Reserved Prefetchable Reserved Reserved Valid A7467-01 4.3.5 Forwarding of 64-Bit Address Memory Transactions The 21555 considers the host and local memory space above the 4 GB boundary to be shared.
Address Decoding the Downstream memory 3 address range must be set to a non-zero value when the upper 32 bits are enabled (a base address of 0 is not allowed). . Figure 10. Dual-Address Transaction Forwarding 264 Byte Boundary 4GB Boundary Base + Offset Translated Base + Offset Primary Address Map Secondary Address Map A7468-01 4.4 I/O Transaction Address Decoding The 21555 provides a mechanism where one BAR on each interface can be configured to be an I/O BAR instead of a memory BAR.
Address Decoding transaction. One pair is used for downstream I/O transactions and one pair is used for upstream I/O transactions. The downstream registers can only be accessed from the primary interface, and the upstream registers can only be accessed from the secondary interface. Their function is similar, so only the downstream case is discussed. The Downstream I/O Address register contains the address used when the transaction is initiated on the secondary bus.
Address Decoding 4.4.2 Subtractive Decoding of I/O Transactions The 21555 can be enabled to subtractively decode I/O transactions and forward these transactions to the opposite bus. No address translation is performed on subtractively decoded I/O transactions. The transaction is treated by the 21555 as a delayed transaction. Note: Even when a subtractively-decoded delayed transaction is queued, the 21555 continues to respond to the transaction on the initiator bus with subtractive timing.
Address Decoding Accesses to the 21555 configuration space are not ordered with respect to transactions in the 21555 queues. That is, the 21555 responds immediately to configuration transactions regardless of what transactions exist in the upstream and downstream queues. Exceptions to this are configuration accesses that result in the initiation of configuration and I/O transactions by the 21555.
Address Decoding The 21555 provides a semaphore method that may be used to guarantee atomicity of the address and data register accesses using the Upstream Configuration Own bit and Downstream Configuration Own bit. Atomicity of these accesses is not guaranteed in hardware. When the corresponding Configuration Enable bit is not set, the Own bit is treated as reserved. The following procedure should be used for downstream transactions: 1.
Address Decoding 4.6 21555 Bar Summary Table 12 shows a summary of the 21555 BARs. Table 12.
PCI Bus Transactions 5 This chapter presents the theory of operation information about PCI transactions. See Chapter 16 for specific information about PCI registers. The following sections are discussed: • • • • • • Section 5.2, “Posted Write Transactions” on page 50. Section 5.3, “Delayed Write Transactions” on page 54. Section 5.4, “Delayed Read Transactions” on page 55. Section 5.5, “64-Bit and 32-Bit Transactions Initiated by the 21555” on page 59. Section 5.6, “Target Terminations” on page 60.
PCI Bus Transactions 5.2 Posted Write Transactions This section discusses the following Posted Write Transactions: • • • • Section 5.2.1, “Memory Write Transactions” on page 51. Section 5.2.2, “Memory Write and Invalidate Transactions” on page 51. Section 5.2.3, “64-bit Extension Posted Write Transaction” on page 52. Section 5.2.4, “Write Performance Tuning Options” on page 52.
PCI Bus Transactions 5.2.1 Memory Write Transactions As a target, the 21555 disconnects memory write transactions at the following address boundaries: • An aligned 4KB address boundary. • An aligned page address boundary for upstream transactions falling in the Upstream Memory 2 address range. • An aligned cache line boundary, when the MW disconnect bit is set in configuration space.
PCI Bus Transactions When any of these conditions is not met, the 21555 uses the memory write command. When a subsequent cache line in the transaction does not have all bytes enabled, the 21555 terminates the MWI transaction and delivers the remaining data using a memory write command. The 21555 continues the MWI transaction as long as a full cache line is posted in the posted write queue. A a full cache line corresponds to the cache line size of the target bus.
PCI Bus Transactions 5.2.4.3 Write-Through When the 21555 is able to obtain access to the target bus and start transferring write data to the target before the transaction has been terminated on the initiator bus, it automatically enters flow-through mode. In flow-through mode, the 21555 can sustain long write bursts as long as a queue-empty condition is detected in posted write buffers or until an aligned disconnect boundary is reached.
PCI Bus Transactions 5.3 Delayed Write Transactions The 21555 uses delayed transactions when forwarding I/O writes from one PCI interface to the other. Delayed transactions are also used for CSR or configuration register writes that cause the 21555 to initiate a transaction on the opposite interface, such as: • CSR or configuration register write access that causes the 21555 to initiate a configuration write transaction. • CSR write access that causes the 21555 to initiate an I/O write transaction.
PCI Bus Transactions When the initiator repeats the transaction using the same address, bus command, write data, and byte enables, then the 21555 returns the appropriate target termination when ordering rules allow. Otherwise, the 21555 continues to return target retry. The target terminations are listed in Table 13. Table 13. Delayed Write Transaction Target Termination Returns Target Bus Response Initiator Bus Response TRDY# TRDY# and STOP# when multiple data phases are requested.
PCI Bus Transactions The 21555 requests the target bus and initiates the delayed read transaction as soon as the 21555 ordering rules allow. See Section 5.7. When the transaction is a nonprefetchable read as described in Section 5.4.1, the 21555 requests only a single Dword of data. When the transaction is a memory read, the 21555 follows the prefetch rules outlined in Section 5.4.2.
PCI Bus Transactions 5.4.2 Prefetchable Reads The following transactions are considered by the 21555 to be prefetchable read transactions: • Transactions using the memory read line command. • Transactions using the memory read multiple command. • Transactions using the memory read command that address a range configured as prefetchable. During a prefetchable read, the 21555 speculatively reads data from the target before the initiator explicitly requests it.
PCI Bus Transactions When using the Quadword boundary, REQ64# asserts every time the transaction is Quadword-aligned (AD[3:0] = x000b). In some cases, the address is only 2 Dwords away from a cache line boundary, or a 4KB boundary. This means that if an ACK64# is not received from the target, another transaction may be necessary to get the high Dword (since FRAME# is only asserted for one cycle, indicating a single data phase).
PCI Bus Transactions 5.4.4.3 Read Queue Full Threshold Tuning The 21555 implements read queue management control bits for each read data queue in the Chip Control 1 configuration register. These bits specify at what read-queue threshold the 21555 initiates a delayed prefetchable read transaction on the target bus. Use of these bits can minimize fragmentation of prefetchable read bursts.
PCI Bus Transactions 5.6 Target Terminations This section describes the following target retries, target disconnects, and target aborts received and returned by the 21555. • Section 5.6.1, “Target Terminations Returned by the 21555” on page 60. • Section 5.6.2, “Transaction Termination Errors on the Target Bus” on page 61. • Section 5.6.2, “Transaction Termination Errors on the Target Bus” on page 61. 5.6.
PCI Bus Transactions 5.6.2 Transaction Termination Errors on the Target Bus When the 21555 detects a target abort on the target bus, the 21555 sets the Received Target Abort in the Primary and Secondary Status register. See Table 62, “Primary and Secondary Status Registers” on page 150. In addition, the 21555: • For delayed transactions, returns a target abort to the initiator and sets the Signaled Target Abort bit in the Primary and Secondary Status register.
PCI Bus Transactions • A target retry in response to a posted write is allowed, but only due to temporary conditions, such as a buffer-full condition. The ordering rules apply to transactions crossing the bridge in the same direction. — A posted write. — A delayed write and read request. — A delayed write and read completion. Delayed completions cross the bridge in the opposite direction of its respective delayed request. Table 16 lists the 21555 transaction ordering rules. Table 16.
PCI Bus Transactions Note: Performance may be affected if the Delayed Transaction Order Control bit is set, as the 21555 deasserts the PCI request signal between transactions. When the Delayed Transaction Order Control bit is zero, the 21555 may keep REQ# asserted after a target retry or target disconnect if another transaction is pending. See Table 77, “Chip Control 0 Register” on page 156.
Initialization Requirements 6 This chapter presents the theory of operation information about the 21555 initialization requirements. See Chapter 16 for specific information about the initialization registers. 6.1 Power Management, Hot-Swap, and Reset Signals Table 17 describes the power management, hot-swap, and reset signals. Table 17. Power Management, Hot-Swap, and Reset Signals (Sheet 1 of 2) Signal Name l_stat Type Description TS CompactPCI hot-swap local status pin.
Initialization Requirements Table 17. Power Management, Hot-Swap, and Reset Signals (Sheet 2 of 2) Signal Name Type Description Secondary bus power management event. The subsystem asserts this signal to the 21555 to indicate that it is signaling a power management event. The 21555 conditionally asserts p_pme_l when s_pme_l is asserted low. s_pme_l I When the subsystem does not generate power management events, this signal can also be used for a subsystem status signal.
Initialization Requirements The secondary reset output, s_rst_l, is asserted and remains asserted when any of the following are true: • • • • • The 21555 primary reset input, p_rst_l, is asserted. The 21555 secondary reset input, s_rst_in_l, is asserted. The Secondary Reset bit in the Table 123, “Reset Control Register” on page 188 is set to a 1. The Chip Reset bit in the Table 123, “Reset Control Register” on page 188 is set to a 1. A power management transition from D3hot to D0 occurs (see Section 6.4.
Initialization Requirements 6.2.1 Central Function During Reset The 21555 is selected to be the secondary bus central function when it detects pr_ad[6] low when s_rst_l is asserted. When the 21555 detects this condition, it immediately drives s_ad, s_cbe_l, and s_par low and tristates secondary bus control signals for the duration of secondary bus reset. When the 21555 implements a 64-bit secondary interface, it also asserts s_req64_l, but tristates all other secondary bus 64-bit extension signals.
Initialization Requirements 6.3.1 With SROM, Local, and Host Processors The following is the 21555 initialization procedure using all configuration mechanisms: 1. Serial Preload Upon deassertion of p_rst_l or completion of chip reset, the 21555 automatically starts the serial load sequence when a SROM is present. The serial load takes approximately 18700 primary bus clock (p_clk) cycles (550 SROM clock cycles).
Initialization Requirements The remainder of the 21555 configuration proceeds as described in Section 6.3.1. 6.3.3 Without Local Processor Initialization of the 21555 is possible without a local processor, or without local processor intervention. Serial preload is still performed as described in (Section 16.10). However, the serial load must clear the Primary Lockout Reset Value bit to allow access of configuration registers from the primary interface.
Initialization Requirements 6.4.1 Transitions Between Power Management States The 21555 is put into a different power state by writing the Power State bits in the Power Management Control and Status configuration register. Table 19 shows the actions that the 21555 takes when transitioning between power states. Although any transition to a lower power state is allowed, all transitions to a higher power state must go to D0. Table 19.
Initialization Requirements 6.4.3 Power Management Data Register The PCI Power Management specification defines an optional data register that can be used for static or dynamic data reporting. A Data Select field in the Power Management Control and Status register selects the type of data to be reported. A Data Scale register provides the scale factor for this data. The 21555 allows implementation of this Data register for static data reporting for the subsystem.
Initialization Requirements A CompactPCI hot-swap card also implements an indicator LED. When the LED is on, this indicates that the board can be removed from the slot. Software may choose to flash the LED to indicate an intermediate state as well. The CompactPCI hot-swap controller controls the state of the LED. The 21555 multiplexes the microswitch state input and the LED control output onto a single shared pin, l_stat.
Initialization Requirements The 21555 enters the Signal Insertion state from the Serial Preload state when the following conditions are satisfied: • Serial preload is complete. • Primary Lockout Reset Value bit cleared. • Ejector handle is closed (micro-switch opens, and l_stat is sampled low). The card has now been completely seated and the local initialization is complete. The card is ready for host configuration and initialization. The 21555 sets the INS_STAT bit and asserts p_enum_l to the host.
Initialization Requirements When the INS_STAT bit is cleared, the card is ready for normal operation. When l_stat continues to be sampled low, that indicates that the ejector handle is closed (and the micro-switch is open), meaning the card remains fully inserted. The 21555 enters the Normal Operation state. Figure 12.
Initialization Requirements However, when the 21555 samples l_stat high once the INS_STAT bit is cleared, this indicates that the ejector handle has been opened. This is interpreted as a removal event, and the 21555 enters the Signal Removal state instead. The same is true when the 21555 samples l_stat high while in the Normal Operation state. When the 21555 enters the Signal Removal state, the REM_STAT bit is set and p_enum_l is asserted to indicate that a removal request is being made.
7 Clocking The 21555 supports two clock inputs, p_clk and s_clk. The signal p_clk corresponds to the primary interface and s_clk corresponds to the secondary interface. Both clocks must adhere to the PCI Local Bus specification. The 21555 may operate in either synchronous or asynchronous mode. The 21555 starts in asynchronous mode during reset, but can switch to synchronous mode after reset when pr_ad[4] is sampled low during reset. In asynchronous mode, p_clk and s_clk can be asynchronous to each other.
Clocking Table 20. Primary and Secondary PCI Bus Clock Signals (Sheet 2 of 2) Signal Name s_clk I/O Description I Secondary interface PCI CLK. This signal provides timing for all transactions on the secondary PCI bus. All secondary PCI inputs are sampled on the rising edge of s_clk, and all secondary PCI outputs are driven from the rising edge of s_clk. The 21555 operates in a frequency range from 0 MHz to 66 MHz in synchronous mode.
Clocking 7.3 66 MHz Support The 21555 supports 66 MHz operation. It has two pins, p_m66ena and s_m66ena, that indicate whether the primary and secondary bus are operating at 66 MHz, respectively. Signal p_m66ena is an input-only pin. • When sampled high, the primary bus is assumed to be operating at 66 MHz. • When sampled low, the primary bus must be operating at or below 33 MHz. Signal s_m66ena is an input/ open-drain pin. • When sampled high, the secondary bus is assumed to be operating at 66 MHz.
Parallel ROM Interface 8 This chapter presents the theory of operation information about the 21555 Parallel ROM (PROM) interface. See Chapter 16 for specific information about the PROM registers. The 21555 supports the attachment of a standard PROM or EPROM with the addition of a small amount of external logic. Flash ROMs compatible with Intel’s 28F00x can be used with this interface. The 21555 supports a PCI expansion ROM BAR on its primary interface with ROM sizes of 4KB to 16MB.
Parallel ROM Interface Table 21. PROM Interface Signals (Sheet 1 of 2) Signal Name Type Description These signals interface to both the serial and parallel external ROM circuitry and have multiple functions. The signals pr_ad[7:0] serve as multiplexed address/data for the PROM and are latched externally in the following sequence: • Address [23:16] during the first address cycle. • Address [15:8] during the second address cycle. • Address [7:0] during the third address cycle.
Parallel ROM Interface Table 21. PROM Interface Signals (Sheet 2 of 2) Signal Name Type Description pr_ale_l O PROM address latch enable/chip select decoder enable. The signal pr_ale_l is used to enable the PROM address latches. The 21555 asserts pr_ale_l low when it drives the first eight bits of the 24-bit address on pr_ad[7:0], and keeps it asserted until the last eight bits of the address are driven. The address is shifted through three octal D-registers while pr_ale_l is low.
Parallel ROM Interface 8.2 Parallel and Serial ROM Connection Figure 14 shows how a parallel and serial ROM can be connected to the 21555. This figure illustrates the connection of a 16MB ROM. When a smaller ROM is used, the address registers corresponding to the upper address bits can be eliminated, as those upper address bits are ignored. . Figure 14.
Parallel ROM Interface When a byte read of the PROM is performed, the 21555 follows this sequence on the ROM interface, also shown in Figure 15. 1. The 21555 drives address bits [23:16] on the pr_ad[7:0] pins and asserts pr_ale_l to enable the address registers. 2. The 21555 drives pr_clk high, latching address bits [23:16] into the first external register. 3. The 21555 drives pr_clk low. 4. The 21555 drives address bits [15:8] on the pr_ad[7:0] pins. 5.
Parallel ROM Interface 8.4 PROM Write by CSR Access Byte writes of the PROM can be performed by CSR access of the Table 112, “ROM Control Register” on page 178, Table 111, “ROM Address Register” on page 178, and Table 110, “ROM Data Register” on page 177. A byte write is performed as follows: 1. The initiator writes the byte address offset to the ROM Address register. 2. The initiator writes one byte of write data into the ROM Data register. 3.
Parallel ROM Interface . Figure 16. PROM Write Timing p_clk pr_clk pr_ad[7:0] d[7:0] A3 A2 A1 A3 A2 A1 = Address[7:00] A3 A2 = Address[15:8] Write Data [7:0] pr_cs_l pr_wr_l pr_ale_l a[7:0] a[15:8] a[23:16] A3 = Address[23:16] A7471-01 8.5 PROM Dword Read A Dword read is performed on the PROM interface when a read is initiated on the primary bus whose address falls into the address range defined by the Table 107, “Primary Expansion ROM BAR” on page 175.
Parallel ROM Interface 8.6 Access Time and Strobe Control The 21555 controls both the access time and the read and write strobe timing through the ROM Setup CSR. The access time is specified as a multiple of the p_clk signal and must be set to 8, 16, 64, or 256 times the length of a p_clk cycle when p_clk is operating at 33 MHz or below, and 16, 32,128, or 512 times the length of a p_clk cycle when p_clk is operating above 33 MHz. This specifies the number of p_clk cycles that the 21555 asserts pr_cs_l.
Parallel ROM Interface 8.7 Attaching Additional Devices to the ROM Interface The 21555 allows additional devices to be attached to the ROM interface. Two ROM interface signals are slightly redefined to support multiple devices by setting the Multiple Device Enable bit in the Chip Control 0 configuration register. In this mode, the maximum ROM size is reduced because the upper address lines are used to decode device select lines.
Parallel ROM Interface . Figure 18. Attaching Multiple Devices on the ROM Interface 21555 sr_cs sr_do pr_ad[7:0] pr_wr_l pr_rd_l pr_ale_l Serial ROM sr_cs sr_ck sr_di pr_ad[0] pr_ad[1] pr_ad[2] d[7:0] W E# Parallel ROM O E# en 8-bit register a[7:0] en 8-bit register a[15.
9 Serial ROM Interface This chapter presents the theory of operation information about the 21555 Serial ROM (SROM) interface. See Chapter 16 for specific information about the SROM registers. The serial ROM interface is used to preload data into the 21555 configuration registers with vendor-specific values. The format for the serial ROM data is given in Section 9.3. The SROM can be support the Vital Product Data (VPD) interface as described in Chapter 15.
Serial ROM Interface 9.3 SROM Configuration Data Preload Format Some fields of the 21555 configuration registers may be preloaded using the SROM interface. The first two bits read from the SROM after the completion of chip reset indicate whether a register preload should be performed. When the first two bits read as 10b, an auto-load sequence is initiated.
Serial ROM Interface Prior to a SROM write or write all transaction, the 8-bit write data must be written in the ROM Data CSR. To initiate the SROM access, the SROM Start bit in the ROM Control CSR is written with a 1 (the PROM Start bit must be written to a 0 with this access). The 21555 then initiates the SROM access. When the SROM access is complete, the 21555 automatically clears the SROM Start bit. When the operation is a read, the data then can be read from the ROM Data register.
Serial ROM Interface Note: When a SROM access using the CSR mechanism is attempted when the SROM is not implemented, the ROM interface may hang. This prevents access to any PROMs that may be present. A chip reset may be needed to put the ROM interface in an operational state . Figure 19. SROM Write All Timing Diagram pr_ad[0] (sr_ck) sr_cs pr_ad[1] (sr_di) 1 0 0 0 1 X X D7 D1 D0 pr_ad[2] (sr_do) A7476-01 Figure 20.
Serial ROM Interface Figure 22. SROM Erase Timing Diagram pr_ad[0] (sr_ck) sr_cs 1 pr_ad[1] (sr_di) 1 A8 1 A0 A7479-01 Figure 23. SROM Erase All Operation pr_ad[0] (sr_ck) sr_cs pr_ad[1] (sr_di) 1 0 0 1 0 A7480-01 Figure 24.
10 Arbitration This chapter describes the arbitration signals. It also describes how the 21555 implements primary and secondary PCI bus arbitration. See Chapter 16 for specific information about the Arbiter registers. 10.1 Primary PCI Bus Arbitration Signals Table 23 describes the primary PCI bus arbitration signals. Table 23. Primary PCI Bus Arbitration Signals Signal Name 10.2 Type Description p_gnt_l I Primary PCI bus GNT#.
Arbitration 10.3 Primary PCI Bus Arbitration The 21555 implements primary PCI bus request and grant pins, p_req_l and p_gnt_l, that interface to an external primary bus arbiter. These pins are used when the 21555 wants to initiate a transaction on the primary PCI bus. The 21555 asserts p_req_l when a posted write or delayed transaction is queued in upstream buffers.
Arbitration . Figure 25. Secondary Arbiter Example m2 lpg m1 m0 B m4 m3 m5 m8 B = 21555 mx = master # x lpg = low priority group Arbiter Control Register = 1000000111b m6 m7 A7492-01 Each bus master, including the 21555, may be configured to be in either the low priority group or the high priority group by setting the corresponding priority bit in the Arbiter Control register in device-specific configuration space. When the bit is set to a one, the master is assigned to the high priority group.
Arbitration The 21555’s internal arbiter may be programmed to park the secondary PCI bus either at the last master to use the bus, or always on the 21555. In the former case, an initiator's secondary bus grant remains asserted unless and until another initiator has asserted its secondary bus request. In the latter case, when no requests are asserted once a transaction has been initiated, the bus grant is withdrawn from the last master and is asserted internally to the 21555.
Interrupt and Scratchpad Registers 11 This chapter presents the theory of operation information about the 21555 interrupt handling and about the 32-bit scratchpad registers. See Chapter 16 for specific information about these registers. 11.1 Primary and Secondary PCI Bus Interrupt Signals Table 26 describes the primary and secondary PCI bus interrupt signals. Table 26. Primary and Secondary PCI Bus Interrupt Signals Signal Name Type Description Primary PCI bus interrupt.
Interrupt and Scratchpad Registers — Cleared by writing a 1 to the corresponding status bit in the Upstream Page Boundary IRQ 0 or 1 registers. — Asserts s_inta_l when the corresponding mask bit is zero. • A subsystem event is indicated by a rising edge on s_pme_l. — Cleared by writing a 1 to the corresponding status bit in the Chip Status CSR. — Asserts p_inta_l when the corresponding mask bit is zero. • A power management transition from state D1 or D2 to state D0 occurs.
Interrupt and Scratchpad Registers 11.3 Doorbell Interrupts A 16-bit software controlled interrupt request register and an associated 16-bit mask register is implemented for each interface (primary and secondary). Each register is byte addressable for use as two sets of 8-bit interrupt request and interrupt mask registers for each interface (four in all) if desired. These registers can be accessed from the primary or secondary interface of the 21555, in either memory space or I/O space.
Error Handling 12 This chapter presents the theory of operation information about the 21555 Error handling capability. See Chapter 16 for specific information about the Error registers. 12.1 Error Signals This section describes both the primary and secondary PCI bus error signals. 12.1.1 Primary PCI Bus Error Signals Table 27 describes the primary PCI bus error signals. Table 27. Primary PCI Bus Error Signals Signal Name p_perr_l Type STS Description Primary PCI interface PERR#.
Error Handling 12.1.2 Secondary PCI Bus Error Signals Table 28 describes the secondary PCI bus error signals. Table 28. Secondary PCI Bus Arbitration Signals Signal Name s_perr_l Type STS Description Secondary PCI interface PERR#. Signal s_perr_l is asserted when a data parity error is detected for data received on the secondary interface. The timing of s_perr_l corresponds to s_par driven one clock cycle earlier, and s_ad driven two clock cycles earlier.
Error Handling 12.2 Parity Errors The 21555 checks, forwards, and generates parity on both the primary and secondary buses. When forwarding transactions, the 21555 forwards the data parity condition as queued, whether it is bad parity or good parity. Table 29 describes the 21555’s responses to parity errors. Table 29. Parity Error Responses (Sheet 1 of 3) Type of Error Type of Transaction PER† P|S Action Taken • Responds normally to transaction. 0|— • Sets primary Detected Parity Error bit.
Error Handling Table 29. Parity Error Responses (Sheet 2 of 3) Type of Error Type of Transaction PER† P|S 0|— Downstream Delayed Write Action Taken • Queues and forwards transaction with parity error. • Sets primary Parity Error Detected bit. • Returns TRDY# (and STOP# when multiple data phases requested). 1|— • Transaction not forwarded. • Sets primary Parity Error Detected bit. • Asserts p_perr_l. 0|— 1|— Upstream Delayed Write • Transaction completes normally on primary bus.
Error Handling Table 29. Parity Error Responses (Sheet 3 of 3) Type of Error Type of Transaction PER† P|S Action Taken —|0 Transaction completes normally on secondary bus. —|1 Downstream Posted Write • Transaction completes on secondary bus. • Sets secondary Data Parity Detected bit when s_perr_l is asserted. • Transaction completes on secondary bus. 1|1 • Sets secondary Data Parity Detected bit when s_perr_l is asserted. • Asserts p_serr_l when no parity error detected on primary bus.
Error Handling 12.3 System Error (SERR#) Reporting The 21555 has two system error pins. Signal p_serr_l reports system errors on the primary interface, and s_serr_l reports system errors on the secondary interface. For the 21555 to assert the SERR# signal for that interface, the SERR# Enable must be set in the Command Configuration register corresponding to that interface. In addition, each device-specific condition has a disable bit for each interface.
JTAG Test Port 13 This chapter presents the theory of operation information about the 21555 JTAG interface. See Chapter 16 for specific information about the JTAG registers. The 21555’s implementation of the JTAG test port is according to IEEE Std. 1149.1, IEEE Standard Test Access Port and Boundary-Scan Architecture. The JTAG test port consists of the following: • • • • • A 5-signal test port interface. A test access port controller. An instruction register. A bypass register. A boundary-scan register.
JTAG Test Port 13.2 Test Access Port Controller The test access port controller is a finite-state machine that interprets IEEE 1149.1 protocols received through the tms signal. The state transitions in the controller are caused by the tms signal on the rising edge of tck. In each state, the controller generates appropriate clock and control signals that control the operation of the test features. After entry into a state, test feature operations are initiated on the rising edge of tck. 13.2.
I2O Support 14 This chapter presents the theory of operation information about the 21555 I20 support. See Chapter 16 for specific information about I20 registers. The 21555 implements an I2O messaging unit to allow passing of I2O messages between the host system and the local subsystem which is called IOP in I2O nomenclature.
I2O Support The 21555 implements the following hardware for the Inbound Queue: • • • • • • • Table 85, “I2O Inbound Queue” on page 166 register at CSR offset 40h. Table 87, “I2O Inbound Free_List Head Pointer” on page 167 at CSR offset 48h. Table 88, “I2O Inbound Post_List Tail Pointer” on page 167 at CSR offset 4Ch. Table 91, “I2O Inbound Post_List Counter” on page 168 at CSR offset 58h. Table 92, “I2O Inbound Free_List Counter” on page 168 at CSR offset 5Ch.
I2O Support processor removes the message from the Inbound Post_List, it must write bit 31 of the Inbound Post_List counter with a 0, which causes the 21555 to decrement the Inbound Post_List counter by 1. When the counter decrements to zero, the 21555 deasserts s_inta_l, indicating that there are no more posted MFAs in the Inbound Queue. Once the local processor consumes the inbound message from the host, it replaces the empty MFA onto the end of the Inbound Free_List.
I2O Support and asserts p_inta_l to indicate to the host processor that one or more MFAs exist in the Outbound Post_List . Signal p_inta_l remains asserted until either the Outbound Post_List Counter is zero and the outbound prefetch buffer empties, or the Outbound Post_List Mask bit is set. The host processor removes the message from the Outbound Post_List by reading the 21555 CSR offset 44h. The 21555 maintains a 2 Dword outbound prefetch buffer to hold the next two MFAs from the Outbound Post_List.
I2O Support • All MFA counters maintained by the 21555 may be individually loaded with any data value by writing a 1 to bit 31 of the corresponding counter Dword offset. When either the Inbound Free_List Counter or the Outbound Post_List Counter is loaded, the 21555 discards any prefetched data in the corresponding prefetch buffer.
VPD Support 15 This chapter presents the theory of operation information about the 21555 Vital Product Data (VPD) support. See Chapter 16 for specific information about the VPD registers. The 21555 provides VPD support through its serial ROM interface. Note that VPD support in the Expansion ROM as described in the PCI Local Bus Specification, Revision 2.2, is transparent to the 21555 and is not described in this document. VPD is stored in the last 3K bits (384 bytes) of the serial ROM.
VPD Support 15.2 Writing VPD Information A write can occur only to the last 2 Kb (256 bytes) of VPD Space. Valid VPD byte addresses for write operations are 17F:080h. To write VPD information from the serial ROM, the following steps must be taken: 1. The VPD data register is written with 4 bytes of data. Byte 0 contains the data to be written to the location referenced by the VPD byte address. The value in bytes 3:1 of the VPD Data register is written to successive byte locations in VPD space. 2.
List of Registers 16 List of Registers This chapter contains reference information about all of the 21555 registers. Table 31 is a cross reference between the sections in this chapter to there accompanying theory of operation chapters. Table 31. Register Cross Reference Table Theory of Operation Chapter Register Reference Information. Chapter 4, “Address Decoding” Section 16.
List of Registers • “Via Setup” refers to the base address setup register corresponding to that BAR 16.2 Configuration Registers Table 32 lists the configuration space address registers. Table 32.
List of Registers Table 32.
List of Registers Table 32.
List of Registers Table 32.
List of Registers Table 32. Configuration Space Address Register (Sheet 5 of 5) Byte Offset (Hex) Reset Value (Hex) Register Name Write Access Preload Read Access EC CompactPCI Hot-Swap Capability Identifier and Next Pointer Register, page 189 06 — Secondary N ED Hot-Swap Cap ID 00 — N N EE CompactPCI Hot-Swap Control Register, page 189 00x1000b — Y N 00000000 — N Y Hot-Swap Next Ptr Hot-Swap Control FF:F0 16.
List of Registers Table 33.
List of Registers Table 33.
List of Registers Table 33.
List of Registers Table 33. CSR Address Map (Sheet 5 of 5) Byte Offset (Hex) Register Name Reset Value Write Access Read Access 0FF:0D0 Reserved 00000000 N Y 1FF:100 Upstream Memory 2 Lookup Table, page 147 Indeterminate Y Y 00000000 N Y Upstream Memory 2 Look-up Table FFF:200 Reserved 16.4 Address Decoding 16.4.1 Primary and Secondary Address This section covers pages 16-130 through 16-140 and includes tables Table 34 through Table 60.
List of Registers Table 34. Primary CSR and Downstream Memory 0 Bara (Sheet 2 of 2) • Primary byte offset: 13:10h • Secondary byte offset: 53:50h The Primary CSR and Downstream Memory 0 BARs map the 21555 registers into primary memory space. They can specify a downstream memory range for forwarding of memory transactions.
List of Registers Table 35. Secondary CSR Memory BARsa (Sheet 2 of 2) • Primary byte offset: 53:50h • Secondary byte offset: 13:10h Bit Name R/W 3 Prefetchable R 11:4 — R Returns zero. 31:12 Base Address R/W Indicate to configuration software the size of the requested memory address range and set the base address of the range. The bits are mappable, and indicates that the 21555 is requesting a 4Kb memory space. a. Description Indicates if this space is prefetchable.
List of Registers Table 37. Downstream I/O or Memory 1 and Upstream I/O or Memory 0 BAR Offsets Downstream I/O or Memory 1 BAR Upstream I/O or Memory 0 BAR Primary byte 1B:18h 5B:58h Secondary byte 5B:58h 1B:18h These registers define forwarding address ranges for downstream or upstream I/O or memory transactions. After reset, they are disabled and return all zeros when read. This register can request a 64, 128, or 256 bytes I/O space. Hardware does not restrict larger I/O windows or 4 KB to 2 GB.
List of Registers Table 38. Downstream Memory 2 and 3 BAR, and Upstream Memory 1 BAR Downstream Memory 2 BAR Offsets Downstream Memory 3 BAR Upstream Memory 1 BAR Primary byte 1F:1Ch 23:20h 5F:5Ch Secondary byte 5F:5Ch 63:60h 1F:1Ch These registers are similar and are described together.
List of Registers Table 39. Upper 32 Bits Downstream Memory 3 Bar • Primary byte offset: 27:24h • Secondary byte offset: 67:64h Bit Name R/W Description This register defines the upper 32 bits of a memory range for downstream forwarding of memory transactions. The lower 32 bits are contained in the Downstream Memory 3 BAR. These bits are used to indicate the size of the requested address range and to set the base address of the range.
List of Registers Table 41. Downstream I/O or Memory 1 and Upstream I/O or Memory 0 Translated Base Register Offsets Downstream I/O or Memory 1 Translated Base Upstream I/O or Memory 0 Translated Base Primary byte 9B:98h A7:A4h Secondary byte 9B:98h A7:A4h CSR byte 06F:06Ch 07B:078h Bit Name R/W Description 5:0 Reserved R Reserved. Returns 0 when read.
List of Registers Table 42. Downstream Memory 0, 2, 3, and Upstream Memory 1 Translated Base Register These registers contain the translated base addresses for their respective downstream and upstream BARs. The base address of the transaction on the initiator bus is replaced by the base address contained in these registers These registers are also mapped in the 21555 I/O and memory CSR space.
List of Registers Table 43. Downstream I/O or Memory 1 and Upstream I/O or Memory 0 Setup Registers These registers may be preloaded by serial ROM or programmed by the local processor before host configuration. Offsets Downstream I/O or Memory 1 Setup Upstream I/O or Memory 0 Setup Primary byte B3:B0h C7:C4h Secondary byte B3:B0h C7:C4h Bit Name R/W 0 Type Selector R/(WS) Description • When 0, the BAR is requesting memory space, or is disabled. • When 1, the BAR is requesting I/O space.
List of Registers Table 44. Downstream Memory 0, 2, 3, and Upstream Memory 1 Setup Registers These registers are used to program the type and size of their respective upstream and downstream BARs.
List of Registers Table 45. Upper 32 Bits Downstream Memory 3 Setup Register This register may be preloaded by serial ROM or programmed by the local processor before host configuration. • Primary byte offset: BF:BCh • Secondary byte offset: BF:BCh Bit Name R/W Description These bits specify upper 32 bits of the size of the address range requested by Downstream Memory 3 BAR. • When a bit is 1, the corresponding bit in Downstream Memory 3 BAR functions as a readable and writable bit.
List of Registers Table 46. Downstream and Upstream Configuration Address Registers This section describes both the downstream and upstream versions of the registers. These registers are also mapped in memory and I/O space.
List of Registers Table 47. Downstream Configuration Data and Upstream Configuration Data Registers These registers are also mapped in memory and I/O space. This register is treated as a reserved register for all memory accesses.
List of Registers Table 48. Configuration Own Bits Register 7:1 Reserved R Read only as 0. Indicates ownership of the Upstream Configuration Address and Upstream Configuration Data registers. Upstream 8 Configuration Own Bit R0TS (S) R(P) • When 0, upstream Configuration Address and Upstream Configuration Data registers are not owned. When read as a 0 from the secondary interface, this bit is subsequently set to a 1 by the 21555 if the Upstream Configuration Control bit is a 1.
List of Registers Table 49. Configuration CSR (Sheet 2 of 2) This register is also mapped in memory and I/O space. • Primary byte offset: 93:92h • Secondary byte offset: 93:92h • CSR byte offset: 013:012h Bit Name R/W Description Enables the 21555 to perform upstream indirect configuration transactions. 9 Upstream Configuration Control R/W • When 0, the 21555 will not initiate a configuration transaction on the primary interface when the Upstream Configuration Data register is accessed.
List of Registers Table 51. Downstream I/O Data and Upstream I/O Data Registers The Downstream I/O Data register is used for I/O transactions to be initiated on the secondary bus, and the Upstream I/O Data register is used for I/O transactions to be initiated on the primary bus. The downstream register can be written from the primary interface only and the upstream register can be written from the secondary interface only.
List of Registers Table 53. I/O CSR • Byte Offset: 027:026h Bit Name R/W Description This bit reflects the status of the Secondary Own bit used for generating I/O transaction on the secondary bus. Downstream I/O Own Bit Status 0 • When 0, the Downstream I/O Address and Downstream I/O Data registers are not owned. R • When 1, the Downstream I/O Address and Downstream I/O Data registers are owned by a master. Enables the 21555 to perform downstream indirect I/O transactions.
List of Registers Table 55. Lookup Table Data Register Table 54 and Table 55 are registers that provide a method for the lookup table to be accessed using I/O transactions, although memory transactions can use either this mechanism or direct access of the lookup table. The lookup table is not byte-writable; byte enables are ignored.
List of Registers Table 57. Primary Interface Configuration Space Address Map Byte 3 Byte 2 Byte 1 Byte 0 Device ID1 Vendor ID1 Primary Status Primary Command Header Type1 Subsystem ID1,2 Primary Min_Gnt2 00h 40h 04h 44h 08h 48h Primary MLT Primary CLS 0Ch 4Ch Subsystem Vendor ID1,2 2Ch 6Ch Cap_Ptr1 34h 74h Primary Interrupt Line 3Ch 7Ch Reserved Primary Max_Lat2 Secondary Offset Revision ID1 Primary Class Code2 BIST1,2 Primary Offset Primary Interrupt Pin 1.
List of Registers 16.5.2 Primary and Secondary Command Registers The register types in this section have separate registers for the primary and secondary interfaces. However, the register description is given once, and applies to both the primary and secondary configuration registers. The primary register controls behavior on the primary interface only, and the secondary register controls behavior on the secondary interface only. Table 61.
List of Registers Table 61. Primary and Secondary Command Registers (Sheet 2 of 2) Offsets Primary Command Secondary Command Primary byte 05:04h 45:44h Secondary byte 45:44h 05:04h Bit Name R/W Description 7 Wait Cycle Control R Reads as zero to indicate the 21555 does not perform address or data stepping. Controls the enable for SERR# on the corresponding interface. SERR# Enable 8 • When 0, SERR# cannot be driven by the 21555.
List of Registers Table 62. Primary and Secondary Status Registers (Sheet 2 of 2) The bits described in Table 62 reflect the status of the 21555 primary interface for the Primary Status register, and of the secondary interface for the Secondary Status register. W1TC indicates that writing a 1 to that bit clears the bit to 0. Writing a 0 has no effect.
List of Registers Table 64. Primary and Secondary Class Code Registers These registers may be preloaded through the serial ROM. The Primary Class Code register may also be programmed by the local processor before host configuration. Offsets Primary Class Code Secondary Class Code Primary byte 0B:09h 4B:49h Secondary byte 4B:49h 0B:09h Bit Name R/W Description 7:0 Prog IF (PIF) PPIF: R/(WS) SPIF: R Reads as zero.
List of Registers Table 66. Primary Latency and Secondary Master Latency Timer Registers Offsets Primary MLT Secondary MLT Primary byte 0Dh 4Dh Secondary byte 4Dh 0Dh Bit 7:0 Name Master Latency Timer R/W Description R/W Master latency timer for the corresponding interface. Indicates the number of PCI clock cycles from the assertion of FRAME# to the expiration of the timer when the 21555 is acting as a master. All bits are writable, resulting in a granularity of 1 PCI clock cycle.
List of Registers Table 69. Subsystem Vendor ID Register • Primary byte offset: 2D:2Ch and 6D:6Ch • Secondary byte offset: 6D:6Ch and 2D:2Ch Bit Name R/W Description 15:0 Subsystem Vendor ID R/(WS) Identifies the vendor of the add-in card or subsystem. This register is initialized by either the local processor or by serial ROM preload. Table 70.
List of Registers Table 73. Primary and Secondary Interrupt Pin Registers Offsets Primary Interrupt Pin Secondary Interrupt Pin Primary byte 3Dh 7Dh Secondary byte 7Dh 3Dh Bit Name R/W Description 7:0 Interrupt Pin R This register indicates which PCI interrupt pin the 21555 uses on the corresponding bus. This is a read-only register and always returns 1 when read indicating that the 21555 uses INTA#. Table 74.
List of Registers 16.5.3 Device-Specific Control and Status Registers This section contains information about the device-specific control and status registers. Table 76. Device-Specific Control and Status Address Map Byte 3 Byte 2 Primary Offset Secondary Offset Chip Control 0 CCh CCh Chip Status D0h D0h Byte 1 Chip Control 1 Byte 0 Table 77. Chip Control 0 Register (Sheet 1 of 4) This register may be preloaded by serial ROM or programmed by the local processor before host configuration.
List of Registers Table 77. Chip Control 0 Register (Sheet 2 of 4) This register may be preloaded by serial ROM or programmed by the local processor before host configuration. • Primary byte offset: CD:CCh • Secondary byte offset: CD:CCh Bit 3 Name Secondary Master Timeout R/W R/W Description Sets the maximum number of PCI clock cycles that the 21555 waits for an initiator on the secondary bus to repeat a delayed transaction request.
List of Registers Table 77. Chip Control 0 Register (Sheet 3 of 4) This register may be preloaded by serial ROM or programmed by the local processor before host configuration. • Primary byte offset: CD:CCh • Secondary byte offset: CD:CCh Bit Name R/W Description Controls prefetching for upstream dual address transactions using the memory read bus command. 8 Upstream DAC Prefetch Disable When 0, prefetching is performed for upstream DAC memory reads.
List of Registers Table 77. Chip Control 0 Register (Sheet 4 of 4) This register may be preloaded by serial ROM or programmed by the local processor before host configuration. • Primary byte offset: CD:CCh • Secondary byte offset: CD:CCh Bit Name R/W Description Allows selection of larger page sizes when programming the page size field in the Chip Control 1 configuration register. 12 LUT Page Size Extension Bit R/W • When 0, page sizes 256 bytes through 4 MB are available in the page size field.
List of Registers Table 78. Chip Control 1 Register (Sheet 1 of 3) This register may be preloaded by serial ROM or programmed by the local processor before host configuration. • Primary byte offset: CF:CEh • Secondary byte offset: CF:CEh Bit 0 Name Primary Posted Write Threshold R/W Description Controls the queue full threshold limit of the downstream posted write queue. When the queue is designated full, the 21555 returns retry to posted writes on the primary bus.
List of Registers Table 78. Chip Control 1 Register (Sheet 2 of 3) This register may be preloaded by serial ROM or programmed by the local processor before host configuration. • Primary byte offset: CF:CEh • Secondary byte offset: CF:CEh Bit Name R/W Description Controls subtractive decoding for downstream and upstream I/O transactions. When the 21555 is enabled to perform subtractive decoding in one direction, those transactions are forwarded to the opposite bus with no address translation.
List of Registers Table 78. Chip Control 1 Register (Sheet 3 of 3) This register may be preloaded by serial ROM or programmed by the local processor before host configuration. • Primary byte offset: CF:CEh • Secondary byte offset: CF:CEh Bit Name R/W Description Enables the I20 message unit. 12 I20_ENA • When 0, the I20 message unit is disabled.
List of Registers Table 79. Chip Status Register All of the following conditions can cause the assertion of p_serr_l or s_serr_l if the corresponding SERR# enable bit is set and the disable bit for this condition is not set. • Primary byte offset: D1:D0h • Secondary byte offset: D1:D0h Bit Name 3 Downstream Posted Write Data Discarded R/W1TC 7:4 Reserved R Reserved. Returns 0 when read.
List of Registers Table 80. Generic Own Bits Register The 21555 implements two generic own bits that can be accessed in either memory or I/O space from either the primary or secondary interface. These bits may be used as an aid to lock resources in software. When a bus master reads the Own bit, it returns 1 if it has already been set, or it returns 0 if the Own bit is available and then automatically sets the bit upon completion of the read. The Own bit is cleared by writing a 1 to the bit.
List of Registers 16.6 I2O Registers This section contains a description of the I2O registers. See Chapter 14 for theory of operation information. Table 81. I2O Outbound Post_List Status Byte Offset: 33:30h Bit Name R/W Description 2:0 Reserved R Reserved. Read only as 0. Reflects the status of the Outbound Post_List. 3 Outbound Post Status • When 0, the Outbound Post_List is empty. The 21555 deasserts p_inta_l (unless it is asserted for other reasons).
List of Registers Table 84. I2O Inbound Post_List Interrupt Mask Byte Offset: 3F:3Ch Bit Name R/W Description 2:0 Reserved R Reserved. Read only as 0. Interrupt mask for Inbound Post_List Status. 3 Inbound Post Mask • When 0, the 21555 asserts s_inta_l when the Inbound Post_List Status bit is a 1. R/W • When 1, the 21555 does not assert s_inta_l when the Inbound Post_List Status bit is a 1. • Reset value is 1 31:4 Reserved R Reserved. Read only as 0. Table 85.
List of Registers Table 87. I2O Inbound Free_List Head Pointer Byte Offsets: 04B:048h Bit Name R/W Description 1:0 Reserved R Reserved. Returns 0 when read. 31:2 Inbound Free Head Ptr R/W Specifies the local memory Dword address of the Inbound Free_List Head Pointer. Increments when the I2O Inbound Queue at offset 40h is read on the primary bus. This pointer automatically wraps when it reaches the upper boundary of the Inbound Free_List. Table 88.
List of Registers Table 91. I2O Inbound Post_List Counter Byte Offsets: 05B:058h Bit Name R/W Description When read, returns the number of entries in the Inbound Post_List. 15:0 Inbound Post Ctr R/(WS) Decrements by 1 when this location is written from the secondary interface with any data value if bit [31] of this register is written with a 0 during the same write. When bit [31] is written with a 1, the 21555 loads the counter with the value written.
List of Registers Table 93. I2O Outbound Post_List Counter Byte Offsets: 063:060h Bit Name R/W Description When read, returns the number of entries in the Outbound Post_List. Increments by 1 when this location is written from the secondary interface with any data value if bit [31] of this register is written with a 0 during the same write. 15:0 Outbound Post Ctr R/(WS) When bit [31] is written with a 1, the 21555 loads the counter with the value written.
List of Registers 16.7 Interrupt Registers This section contains information about interrupt registers. See Chapter 11 for theory of operation information. Table 95. Chip Status CSR Byte Offsets: 083:082h Bit 0 Name PM_D0 R/W R/W1TC Description Power Management Transition to D0. The 21555 sets this bit when it is transitioned from a low power D1 or D2 state to a high power D0 state.
List of Registers Table 97. Chip Clear IRQ Mask Register Byte Offsets: 087:086h Bit Name R/W Description • When 0, signal s_inta_l is asserted on the 21555’s secondary interface when the corresponding chip event bit is a 1, indicating a return of power state to D0. • When 1, the corresponding chip event bit does not generate an interrupt. 0 Clr_D0M R/W1TC Writing a 1 to a bit in this register clears the Chip IRQ Mask bit to 0. Writing a 0 to any bit in this register has no effect.
List of Registers Table 99. Upstream Page Boundary IRQ 1 Register Byte Offset: 08F:08Ch Bit 31:0 Name PAGE1_IRQ R/W Description R/W1TC Each bit in this register corresponds to a page entry in the upper half of the Upstream Memory 2 range. Bit 0 corresponds to the 33rd page, and bit 31 corresponds to the 64th (highest order) page. The 21555 sets the appropriate bit when it successfully transfers data to/ from the initiator that addresses the last Dword in a page.
List of Registers Table 102. Primary Clear IRQ and Secondary Clear IRQ Registers These registers affect primary and secondary interrupts in the same way and are described together. Byte Offset: Bit Name Primary Clear IRQ Secondary Clear IRQ 099:098h 09B:09Ah R/W Description This register controls the state of the Primary or Secondary Interrupt Request bits. • When 0, Does not cause the corresponding primary or secondary interrupt signal to be asserted.
List of Registers Table 104. Primary Clear IRQ Mask and Secondary Clear IRQ Mask Registers These registers affect primary and secondary interrupts in the same way and are described Byte Offset: Bit Name Primary Clear IRQ Mask Secondary Clear IRQ Mask 0A1:0A0h 0A3:0A2h R/W Description • When 0, an interrupt is generated on the 21555’s primary or secondary interface when the corresponding Primary or Secondary Interrupt Request bit is a 1.
List of Registers Table 106. Scratchpad 0 Through Scratchpad 7 Registers (Sheet 2 of 2) 16.9 Bit Name R/W Byte Offset: Description 31:0 SCRATCH3 R/W 0B7:0B4h 32-bit scratchpad register 3. 31:0 SCRATCH4 R/W 0BB:0B8h 32-bit scratchpad register 4. 31:0 SCRATCH5 R/W 0BF:0BCh 32-bit scratchpad register 5. 31:0 SCRATCH6 R/W 0C3:0C0h 32-bit scratchpad register 6. 31:0 SCRATCH7 R/W 0C7:0C4h 32-bit scratchpad register 7. PROM Registers This section describes the six PROM registers.
List of Registers Table 108. Primary Expansion ROM Setup Register This register may be preloaded by serial ROM or programmed by the local processor before host configuration. • Primary byte offset: C3:C0h • Secondary byte offset: C3:C0h Bit Name R/W Description 11:0 Reserved R Reserved. Read only as 0. These bits specify the size of the address range requested by the Primary Expansion ROM Base Address register.
List of Registers Table 109. ROM Setup Register Byte Offsets: 0C9:0C8h Bit Name R/W Description Number of p_clk cycles that pr_cs_l asserts low (in default mode) or pr_ale_l drives high (in multiple device mode) for a PROM or other external device access.
List of Registers Table 111. ROM Address Register Byte Offsets: 0CE:0CCh Bit Name R/W Description Contains the byte address of the PROM read or write access used when the PROM Start bit is set to a 1. Contains the byte address and Opcode used when the Serial ROM Start bit is set to a 1. The byte address is contained on bits [8:0]. The opcode is contained on bits [10:9].
List of Registers Table 112. ROM Control Register (Sheet 2 of 2) Byte Offsets: 0CFh Bit Name R/W Description PROM read/write control bit. This bit may be written with the same CSR access that sets the PROM Start bit. Read/Write 2 R/W Control • When 0, the 21555 performs a read of the PROM when the PROM Start bit is set to a 1. • When 1, the 21555 performs a write of the PROM when the PROM Start bit is set to a 1.
List of Registers Table 113. Mode Setting Configuration Register (Sheet 2 of 2) This register reflects the various mode settings selected by strapping the pr_ad pins, as well as whether the 64-bit extension is enabled. • Primary byte offset: D6h • Secondary byte offset: D6h Bit Name R/W Description Indicates whether s_clk_o is enabled, determined by sampling pr_ad[5] during reset. 3 s_clk_o Enable R • When 0, signal pr_ad[5] was sampled low, causing s_clk_o to be disabled.
List of Registers Table 114. Serial Preload Sequence (Sheet 2 of 3) Not all of the bits in the sequence are used. Bits that are not used must be 0 (zero) Byte offset Description 09h Subsystem ID [7:0] 0Ah Subsystem ID [15:8] 0Bh Primary Minimum Grant 0Ch Primary Maximum Latency 0Dh Secondary Programming Interface 0Eh Secondary Sub-Class Code 0Fh Secondary Base Class Code 10h Secondary Minimum Grant 11h Secondary Maximum Latency 12h Downstream Memory 0 Setup [7:0].
List of Registers Table 114. Serial Preload Sequence (Sheet 3 of 3) Not all of the bits in the sequence are used. Bits that are not used must be 0 (zero) Byte offset Description 2Bh Upstream I/O or Memory 0 Setup [31:24] 2Ch Upstream Memory 1 Setup [7:0]. Bits [0, 7:4] are not loaded and should be 0. 2Dh Upstream Memory 1 Setup [15:8]. Bits [11:8] are not loaded and should be 0.
List of Registers 16.11 Arbiter Control This chapter describes the arbitration control registers. See Chapter 10 for theory of operation information. Table 115. Arbiter Control Register This register may be preloaded by serial ROM or programmed by local processor before host configuration.
List of Registers Table 116. Primary SERR# Disable Register This register may be preloaded by serial ROM or programmed by the local processor before host configuration. This register controls the ability of the 21555 to assert p_serr_l for a particular condition. When the bit is a 0, the assertion of p_serr_l is not masked for this event. When the bit is a 1, the assertion of p_serr_l is masked for this event.
List of Registers Table 117. Secondary SERR# Disable Register Upstream Delayed Read Transaction Discarded 1 R/W Reset value is 0 Upstream Delayed Write Transaction Discarded 2 R/W Disables s_serr_l assertion when the 21555 discards an upstream delayed write transaction request after receiving 224 target retries from the primary bus target.
List of Registers Table 119. Power Management Capabilities Register Bits [14:9,5,2:0] are loadable through the serial ROM or are programmable by the local processor. • Primary byte offset: DF:DEh • Secondary byte offset: DF:DEh Bit Name R/W 2:0 PM Version R/(WS) Description Power Management Version. Loadable by serial ROM. Reset value is Signal 001b to indicate that this device is compliant to the PCI Power Management Interface Specification, Revision 1.1.
List of Registers Table 120. Power Management Control and Status Register Bits [14:13] are loadable by serial ROM or are programmable by the local processor. • Primary byte offset: E1:E0h • Secondary byte offset: E1:E0h Bit Name R/W Description Power State. Reflects the current power state of the 21555. When an unimplemented power state is written to this register, the 21555 completes the write transaction, ignores the write data, and does not change the value of this field.
List of Registers Table 122. Power Management Data Register • Primary byte offset: E3h • Secondary byte offset: E3h Bit Name R/W Description 7:0 PM Data R Power Management Data register. Reflects one of eight bytes loaded by serial ROM, or reads as 0. Bytes are selected by the data select register. Reset value is 00h Table 123.
List of Registers Table 124. CompactPCI Hot-Swap Capability Identifier and Next Pointer Register Offsets HS ECP ID HS Next Pointer Primary byte ECh EDh Secondary byte ECh EDh Bit Name R/W Description 7:0 HS ECP ID R Enhanced capabilities ID. Reads only as 06h to indicate that these are CompactPCI Hot-Swap registers. 7:0 HS NXT PTR R Pointer to next set of ECP registers. Reads only as 0 to indicate that these are the last ECP registers in this list. Table 125.
List of Registers Table 125. CompactPCI Hot-Swap Control Register (Sheet 2 of 2) • Primary byte offset: EF:EEh • Secondary byte offset: EF:EEh Bit Name R/W Description 5:4 Reserved R Returns 0 when read. R/ W1TC Signal p_enum_l Removal Status. The 21555 sets this bit to a 1 when l_stat is sampled high and p_rst_l is deasserted, signaling an impending removal. This bit is cleared when software writes a 1. Clearing this bit causes the 21555 to tristate l_stat. Writing a 0 has no effect.
List of Registers Table 126. JTAG Instruction Register Options (Sheet 2 of 2) The 4-bit instruction register selects the test mode and features. The instruction codes are shown in Table 126. These instructions select and control the operation of the boundary-scan and bypass registers. The instruction register is loaded through the tdi pin. The instruction register has a serial shift-in stage from which the instruction is then loaded in parallel.
List of Registers The group disable number column in TBD shows which group disable bit controls the corresponding output driver. Group disable bits do not affect input-only pins, so those pins have a blank rather than a group number in that column. The group disable control can control pins on either side of where the group disable boundary-scan register cell is placed.
List of Registers Table 131. Vital Product Data (VPD) Address Register • Primary byte offset: E7:E6h • Secondary byte offset: E7:E6h Bit Name R/W Description 8:0 VPD Addr R/W Vital Product Data Address. Contains the VPD byte address of the serial ROM location to be accessed. Valid VPD byte addresses are 17F: 000h. VPD starts at base address 080h in the serial ROM. The VPD byte address contained in this register is added to the VPD base address to obtain the final serial ROM address.
Acronyms • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • A 1D – One-dimensional 2D – Two-dimensional AGP – Accelerated Graphics Port ANSI – American National Standards Institute API – Application Programming Interface BAR – Base Address Register BiST – Built-In Self-Test CLS – Cache Line Sizes CSR – Control and Status Registers DAC – Dual Address Cycle DRC – Delayed Read Completion DRR – Delayed Read Request DWC – Delayed Write Completion DWR – Delayed Write Request ETSI – European Telecom
Acronyms • • • • • • • • • • • • • • • • • MFAs – Message Frame Addresses MPEG – Moving Pictures Experts Group MV – Motion vector MVC – Part Control Number MWI – Memory Write and Invalidate OBMC – Overlapped block motion compensation OS – Operating system PPB – PCI-to-PCI bridge PQFP – Plastic Quad Flat Package quiesced – The PCI card is no longer performing or scheduling transactions.
Index 3-V 15 5-V 15 Primary lockout bit on the PROM_AD 82 Device ID 122 Domains processor 15 Doorbell interrupt functionality 103 A F Add-in card vendors 15 address 33 Address range locations Primary BARs 33 Secondary BARs 33 Address space 34 64-bit 35 expansion ROM decoding 34 type of 130, 132 type of for secondary 131 Address translation 33, 36 Addressing model About the flat 16 Fast Back-to-Back 52 Features of the 21555 15 Flat addressing model 16 B BAR and Memory 0 34 Byte offsets 121 C Cache lin
Primary Lockout bit action before clearing the 130 power management 71 with serial Preload 69 with SROM operation 69, 70 Primary lockout bit type 0 access 44 Processor domains 15 processor 15 I/O Control and Status Register 146 I/O Own Bits Registers 145 JATAG boundary-Scan Register 191 JATAG bypass Register 191 Lookup Table Data Register 147 Lookup Table Offset Register 146 Primary and Secondary CSR I/O BARs 132 Primary CSR and Downstream Memory 0 BAR 130 Secondary CSR Memory BARs 132 Secondary interrupt
