User's Manual

21555 Non-Transparent PCI-to-PCI Bridge User Manual 151
List of Registers
8
Data Parity
Detected
R/
W1TC
This bit is set to a 1 when all of the following are true:
• The 21555 is a master on the corresponding bus.
• PERR# is detected asserted for writes or a parity error is detected
for reads.
• Parity Error Response bit is set in the Primary or Secondary
Command register.
Reset value is 0.
10:9 DEVSEL# timing R
Indicates slowest response to a non configuration command on the
corresponding interface. Reads as 01b to indicate that the 21555
responds no slower than with medium timing.
11
Signaled Target
Abort
R/
W1TC
This bit is set to a 1 when the 21555 is acting as a target on the
corresponding bus and returns a target abort to the initiator.
Reset value is 0.
12
Received Target
Abort
R/
W1TC
This bit is set to a 1 when the 21555 is acting as an initiator on the
corresponding bus and receives a target abort.
Reset value is 0.
13
Received Master
Abort
R/
W1TC
This bit is set to a 1 when the 21555 is acting as an initiator on the
corresponding bus and detects a master abort.
Reset value is 0.
14
Signaled System
Error
R/
W1TC
This bit is set to a 1 when the 21555 has asserted SERR# on the
corresponding bus.
Reset value is 0.
15
Detected Parity
Error
R/
W1TC
This bit is set to a 1 when the 21555 detects an address or data parity
error on the corresponding interface.
Reset value is 0.
Table 63. Revision ID (Rev ID) Register
• Primary byte offset: 08h and 48h
• Secondary byte offset: 08h and 48h
Bit Name R/W Description
7:0 Revision ID R
This register indicates the revision number of this device. The initial revision
reads as 0. Subsequent revisions increment by 1.
Table 62. Primary and Secondary Status Registers (Sheet 2 of 2)
Bit Name R/W Description
The bits described in Table 62 reflect the status of the 21555 primary interface for the Primary Status register,
and of the secondary interface for the Secondary Status register. W1TC indicates that writing a 1 to that bit
clears the bit to 0. Writing a 0 has no effect.
Offsets Primary Status Secondary Status
Primary byte 07:06h 47:46h
Secondary byte 47:46h 07:06h